Fix EXI DO/DI swap: rename nets + swap damping resistors, no copper changes

SP1 DO/DI naming is console-perspective (verified against SD Gecko and
SD2SP2 wiring): pin 6 DO = GC data out = adapter MOSI input, pin 9 DI =
GC data in = adapter MISO output. The design doc's SP1 table had the
roles reversed and the schematic followed it, putting the FPGA's MISO
driver on the GC-driven DO line (bus contention).

Fix keeps all PCB routing identical:
- Swap net names EXI_MOSI(_RAW) <-> EXI_MISO(_RAW) across exi/Fpga/root
  sheets and the PCB (also renames the D2 PUSB3AB6 channel assignments).
- Swap R21 (22R) <-> R25 (33R) identities between the two footprint
  positions so 33R stays on the FPGA-driven MISO line, 22R on the MOSI
  input.
- Correct the SP1 pin table + MISO-tristate note in
  docs/gc_bba_fpga_design.md (root cause).

Resulting board pin map (for the future board PCF): EXI_MOSI = FPGA
pin 4 (IOB_8a, input), EXI_MISO = pin 3 (IOB_9b, output).

Verified: ERC 0, DRC 0 errors with schematic parity 0, netlist shows
J3.6(DO)->R21->pin 4 and J3.9(DI)->R25->pin 3.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

docs/gc_bba_fpga_design.md

@@ -146,10 +146,10 @@ pin 1 is also on the left — numbering does not mirror.
 | 3 | INT | Adapter → GC | Active-low interrupt to GC CPU. Assert when IR & IMR != 0. |
 | 4 | CLK | GC → Adapter | SPI clock, up to 32 MHz, idles HIGH (Mode 3) |
 | 5 | 12V | — | 12 V supply from GC. **Do not connect to FPGA I/O.** Leave unconnected or route to a test point only. |
-| 6 | DO (MISO) | Adapter → GC | Serial data out: adapter drives, GC samples |
+| 6 | DO (MOSI) | GC → Adapter | Serial data out **of the GC** (console-perspective name): GC drives, adapter samples. Verified against SD Gecko/SD2SP2 wiring — do not swap. |
 | 7 | 3.3V | — | 3.3 V supply (~200 mA available combined with pin 8) |
 | 8 | 3.3V | — | 3.3 V supply (parallel with pin 7) |
-| 9 | DI (MOSI) | GC → Adapter | Serial data in: GC drives, adapter samples |
+| 9 | DI (MISO) | Adapter → GC | Serial data in **to the GC** (console-perspective name): adapter drives, GC samples |
 | 10 | CS | GC → Adapter | Chip select, active low. Delineates each transaction. |
 | 11 | GND | — | Signal ground |
 | 12 | GND | — | Signal ground |
@@ -1296,7 +1296,8 @@ with other EXI device implementations without parameterising CPOL/CPHA.
 
 ### MISO tristate
 
-On real hardware, MISO (DO) is tristated when CS is deasserted. Other EXI
+On real hardware, MISO (SP1 pin 9, "DI" in console-perspective naming) is
+tristated when CS is deasserted. Other EXI
 devices on the same bus would otherwise conflict. On this FPGA implementation,
 drive MISO high (not tristated) when CS is deasserted. The iCE40UP5K does
 not easily support pin tristate from user logic — drive high is safe because