Fix EXI DO/DI swap: rename nets + swap damping resistors, no copper changes

SP1 DO/DI naming is console-perspective (verified against SD Gecko and
SD2SP2 wiring): pin 6 DO = GC data out = adapter MOSI input, pin 9 DI =
GC data in = adapter MISO output. The design doc's SP1 table had the
roles reversed and the schematic followed it, putting the FPGA's MISO
driver on the GC-driven DO line (bus contention).

Fix keeps all PCB routing identical:
- Swap net names EXI_MOSI(_RAW) <-> EXI_MISO(_RAW) across exi/Fpga/root
  sheets and the PCB (also renames the D2 PUSB3AB6 channel assignments).
- Swap R21 (22R) <-> R25 (33R) identities between the two footprint
  positions so 33R stays on the FPGA-driven MISO line, 22R on the MOSI
  input.
- Correct the SP1 pin table + MISO-tristate note in
  docs/gc_bba_fpga_design.md (root cause).

Resulting board pin map (for the future board PCF): EXI_MOSI = FPGA
pin 4 (IOB_8a, input), EXI_MISO = pin 3 (IOB_9b, output).

Verified: ERC 0, DRC 0 errors with schematic parity 0, netlist shows
J3.6(DO)->R21->pin 4 and J3.9(DI)->R25->pin 3.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

hardware/re-bba-rb/Fpga.kicad_sch

@@ -3135,7 +3135,7 @@
 		)
 		(uuid "1263a374-a091-46fb-835b-d4113957a468")
 	)
-	(hierarchical_label "EXI_MOSI"
+	(hierarchical_label "EXI_MISO"
 		(shape bidirectional)
 		(at 39.37 143.51 180)
 		(effects
@@ -3388,7 +3388,7 @@
 		)
 		(uuid "b01f227b-7e86-4d0e-83b2-5de764edeec9")
 	)
-	(hierarchical_label "EXI_MISO"
+	(hierarchical_label "EXI_MOSI"
 		(shape bidirectional)
 		(at 39.37 140.97 180)
 		(effects