Fix EXI DO/DI swap: rename nets + swap damping resistors, no copper changes

SP1 DO/DI naming is console-perspective (verified against SD Gecko and
SD2SP2 wiring): pin 6 DO = GC data out = adapter MOSI input, pin 9 DI =
GC data in = adapter MISO output. The design doc's SP1 table had the
roles reversed and the schematic followed it, putting the FPGA's MISO
driver on the GC-driven DO line (bus contention).

Fix keeps all PCB routing identical:
- Swap net names EXI_MOSI(_RAW) <-> EXI_MISO(_RAW) across exi/Fpga/root
  sheets and the PCB (also renames the D2 PUSB3AB6 channel assignments).
- Swap R21 (22R) <-> R25 (33R) identities between the two footprint
  positions so 33R stays on the FPGA-driven MISO line, 22R on the MOSI
  input.
- Correct the SP1 pin table + MISO-tristate note in
  docs/gc_bba_fpga_design.md (root cause).

Resulting board pin map (for the future board PCF): EXI_MOSI = FPGA
pin 4 (IOB_8a, input), EXI_MISO = pin 3 (IOB_9b, output).

Verified: ERC 0, DRC 0 errors with schematic parity 0, netlist shows
J3.6(DO)->R21->pin 4 and J3.9(DI)->R25->pin 3.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

hardware/re-bba-rb/TODO.md

@@ -6,18 +6,25 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
 
 ## Critical — must fix before (or with) next fab
 
-- [ ] **EXI DO/DI swapped at J3** (`exi.kicad_sch`). YAGCD SP1 naming is
-      console-perspective: pin 6 `DO` = GC data **out** → adapter's MOSI
-      *input*; pin 9 `DI` = GC data **in** ← adapter's MISO *output*. Board has
-      J3.6 → EXI_MISO (FPGA output — bus contention with the GC driver) and
-      J3.9 → EXI_MOSI. Verified via SD Gecko (MC pin 5 DO → SD CMD input) and
-      SD2SP2 (DO → OR gate → SD CMD).
-      - [ ] Fix the SP1 pin table in `docs/gc_bba_fpga_design.md` (§ SP1
-            pinout, "DO (MISO) Adapter → GC" is backwards — root cause).
-      - [ ] Fix schematic labels (or PCB routing) so names match reality.
-      - [ ] Decide: keep current copper and swap in `synth.py` pin constraints
-            (both FPGA pins are plain IOBs: pin 3 = IOB_9b, pin 4 = IOB_8a),
-            or re-route. Existing boards are rescuable in constraints alone.
+- [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
+      YAGCD SP1 naming is console-perspective: pin 6 `DO` = GC data **out** →
+      adapter's MOSI *input*; pin 9 `DI` = GC data **in** ← adapter's MISO
+      *output* (verified via SD Gecko: MC pin 5 DO → SD CMD input; SD2SP2:
+      DO → OR gate → SD CMD). Fix applied as a pure rename/identity swap:
+      - [x] SP1 pin table in `docs/gc_bba_fpga_design.md` corrected (was the
+            root cause) + MISO-tristate note updated.
+      - [x] Net names EXI_MOSI(_RAW) ↔ EXI_MISO(_RAW) swapped across
+            `exi.kicad_sch`, `Fpga.kicad_sch`, root sheet, and the PCB — this
+            also swaps the D2 (PUSB3AB6) channel assignments by name.
+      - [x] R21 (22 Ω) ↔ R25 (33 Ω) identities swapped between the two
+            positions so 33 Ω stays on the FPGA-driven MISO line and 22 Ω on
+            the MOSI input.
+      - [x] Verified: ERC 0, DRC 0 (incl. schematic parity 0), netlist:
+            J3.6(DO)→R21(22Ω)→**FPGA pin 4 (IOB_8a) = EXI_MOSI in**;
+            J3.9(DI)→R25(33Ω)→**FPGA pin 3 (IOB_9b) = EXI_MISO out**.
+      - [ ] Use this final pin map when writing the board PCF (see Broader
+            items): MOSI = pin 4, MISO = pin 3, CLK = 44 (G6), CS = 45,
+            INT = 46.
 - [ ] **W5100S MDI termination network missing** (`ethernet.kicad_sch`).
       Per WIZnet W5100S reference schematic: 49.9 Ω from each of
       TXOP/TXON/RXIP/RXIN to a common node with 0.1 µF to GND, placed near the