Fix EXI DO/DI swap: rename nets + swap damping resistors, no copper changes

SP1 DO/DI naming is console-perspective (verified against SD Gecko and
SD2SP2 wiring): pin 6 DO = GC data out = adapter MOSI input, pin 9 DI =
GC data in = adapter MISO output. The design doc's SP1 table had the
roles reversed and the schematic followed it, putting the FPGA's MISO
driver on the GC-driven DO line (bus contention).

Fix keeps all PCB routing identical:
- Swap net names EXI_MOSI(_RAW) <-> EXI_MISO(_RAW) across exi/Fpga/root
  sheets and the PCB (also renames the D2 PUSB3AB6 channel assignments).
- Swap R21 (22R) <-> R25 (33R) identities between the two footprint
  positions so 33R stays on the FPGA-driven MISO line, 22R on the MOSI
  input.
- Correct the SP1 pin table + MISO-tristate note in
  docs/gc_bba_fpga_design.md (root cause).

Resulting board pin map (for the future board PCF): EXI_MOSI = FPGA
pin 4 (IOB_8a, input), EXI_MISO = pin 3 (IOB_9b, output).

Verified: ERC 0, DRC 0 errors with schematic parity 0, netlist shows
J3.6(DO)->R21->pin 4 and J3.9(DI)->R25->pin 3.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

hardware/re-bba-rb/re-bba-rb.kicad_sch

@@ -611,7 +611,7 @@
 				(justify right)
 			)
 		)
-		(pin "EXI_MISO" bidirectional
+		(pin "EXI_MOSI" bidirectional
 			(at 55.88 81.28 0)
 			(uuid "0dcf5cdd-0199-4cd1-9b91-0a62b49304f2")
 			(effects
@@ -621,7 +621,7 @@
 				(justify right)
 			)
 		)
-		(pin "EXI_MOSI" bidirectional
+		(pin "EXI_MISO" bidirectional
 			(at 55.88 83.82 0)
 			(uuid "4fb4e7d3-76e2-41e1-8083-ce5f6cb6c061")
 			(effects
@@ -1199,7 +1199,7 @@
 				(justify left)
 			)
 		)
-		(pin "EXI_MISO" bidirectional
+		(pin "EXI_MOSI" bidirectional
 			(at 104.14 81.28 180)
 			(uuid "0979d259-b2b8-44f3-968b-ffbc5fbcbaaa")
 			(effects
@@ -1209,7 +1209,7 @@
 				(justify left)
 			)
 		)
-		(pin "EXI_MOSI" bidirectional
+		(pin "EXI_MISO" bidirectional
 			(at 104.14 83.82 180)
 			(uuid "5f9986c7-d126-40ae-8e10-3ed93f86746d")
 			(effects