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Fix EXI DO/DI swap: rename nets + swap damping resistors, no copper changes

Browse Source 
SP1 DO/DI naming is console-perspective (verified against SD Gecko and
SD2SP2 wiring): pin 6 DO = GC data out = adapter MOSI input, pin 9 DI =
GC data in = adapter MISO output. The design doc's SP1 table had the
roles reversed and the schematic followed it, putting the FPGA's MISO
driver on the GC-driven DO line (bus contention).

Fix keeps all PCB routing identical:
- Swap net names EXI_MOSI(_RAW) <-> EXI_MISO(_RAW) across exi/Fpga/root
  sheets and the PCB (also renames the D2 PUSB3AB6 channel assignments).
- Swap R21 (22R) <-> R25 (33R) identities between the two footprint
  positions so 33R stays on the FPGA-driven MISO line, 22R on the MOSI
  input.
- Correct the SP1 pin table + MISO-tristate note in
  docs/gc_bba_fpga_design.md (root cause).

Resulting board pin map (for the future board PCF): EXI_MOSI = FPGA
pin 4 (IOB_8a, input), EXI_MISO = pin 3 (IOB_9b, output).

Verified: ERC 0, DRC 0 errors with schematic parity 0, netlist shows
J3.6(DO)->R21->pin 4 and J3.9(DI)->R25->pin 3.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
This commit is contained in:
Dennis Brentjes
2026-07-18 12:36:41 +00:00
parent 4704dfbb36
commit fe96876a80
7 changed files with 94 additions and 86 deletions
Download Patch File Download Diff File Expand all files Collapse all files
CLAUDE.md
+5 -5
View File
@@ -256,11 +256,11 @@ before ordering the interposer PCB; not part of the FPGA build.
`hardware/re-bba-rb/` — the actual adapter PCB (FT2232H + iCE40UP5K + W5100S, `hardware/re-bba-rb/` — the actual adapter PCB (FT2232H + iCE40UP5K + W5100S,
powered from SP1 12 V via buck). **Open findings from the 2026-07-17 hardware powered from SP1 12 V via buck). **Open findings from the 2026-07-17 hardware
review live in `hardware/re-bba-rb/TODO.md`** — read it before editing the review live in `hardware/re-bba-rb/TODO.md`** — read it before editing the
schematics, ordering boards, or writing the board PCF. Highlights: EXI DO/DI are schematics, ordering boards, or writing the board PCF. Highlights: the W5100S
swapped vs the (incorrect) SP1 table in `docs/gc_bba_fpga_design.md` (DO = GC→ MDI 49.9 Ω termination network is missing; the FTDI EEPROM needs its 2.2 k/10 k
adapter = MOSI); the W5100S MDI 49.9 Ω termination network is missing; the FTDI resistors; stock iceprog doesn't match the FTDI pin mapping. (The EXI DO/DI
EEPROM needs its 2.2 k/10 k resistors; stock iceprog doesn't match the FTDI pin swap found in the review is FIXED — SP1 naming is console-perspective, DO = GC→
mapping. adapter = MOSI; board pin map: EXI_MOSI = FPGA pin 4, EXI_MISO = pin 3.)
--- ---
docs/gc_bba_fpga_design.md
+4 -3
View File
@@ -146,10 +146,10 @@ pin 1 is also on the left — numbering does not mirror.
| 3 | INT | Adapter → GC | Active-low interrupt to GC CPU. Assert when IR & IMR != 0. | | 3 | INT | Adapter → GC | Active-low interrupt to GC CPU. Assert when IR & IMR != 0. |
| 4 | CLK | GC → Adapter | SPI clock, up to 32 MHz, idles HIGH (Mode 3) | | 4 | CLK | GC → Adapter | SPI clock, up to 32 MHz, idles HIGH (Mode 3) |
| 5 | 12V | — | 12 V supply from GC. **Do not connect to FPGA I/O.** Leave unconnected or route to a test point only. | | 5 | 12V | — | 12 V supply from GC. **Do not connect to FPGA I/O.** Leave unconnected or route to a test point only. |
| 6 | DO (MISO) | Adapter → GC | Serial data out: adapter drives, GC samples | | 6 | DO (MOSI) | GC → Adapter | Serial data out **of the GC** (console-perspective name): GC drives, adapter samples. Verified against SD Gecko/SD2SP2 wiring — do not swap. |
| 7 | 3.3V | — | 3.3 V supply (~200 mA available combined with pin 8) | | 7 | 3.3V | — | 3.3 V supply (~200 mA available combined with pin 8) |
| 8 | 3.3V | — | 3.3 V supply (parallel with pin 7) | | 8 | 3.3V | — | 3.3 V supply (parallel with pin 7) |
| 9 | DI (MOSI) | GC → Adapter | Serial data in: GC drives, adapter samples | | 9 | DI (MISO) | Adapter → GC | Serial data in **to the GC** (console-perspective name): adapter drives, GC samples |
| 10 | CS | GC → Adapter | Chip select, active low. Delineates each transaction. | | 10 | CS | GC → Adapter | Chip select, active low. Delineates each transaction. |
| 11 | GND | — | Signal ground | | 11 | GND | — | Signal ground |
| 12 | GND | — | Signal ground | | 12 | GND | — | Signal ground |
@@ -1296,7 +1296,8 @@ with other EXI device implementations without parameterising CPOL/CPHA.
### MISO tristate ### MISO tristate
On real hardware, MISO (DO) is tristated when CS is deasserted. Other EXI On real hardware, MISO (SP1 pin 9, "DI" in console-perspective naming) is
tristated when CS is deasserted. Other EXI
devices on the same bus would otherwise conflict. On this FPGA implementation, devices on the same bus would otherwise conflict. On this FPGA implementation,
drive MISO high (not tristated) when CS is deasserted. The iCE40UP5K does drive MISO high (not tristated) when CS is deasserted. The iCE40UP5K does
not easily support pin tristate from user logic — drive high is safe because not easily support pin tristate from user logic — drive high is safe because
hardware/re-bba-rb/Fpga.kicad_sch
+2 -2
View File
@@ -3135,7 +3135,7 @@
) )
(uuid "1263a374-a091-46fb-835b-d4113957a468") (uuid "1263a374-a091-46fb-835b-d4113957a468")
) )
(hierarchical_label "EXI_MOSI" (hierarchical_label "EXI_MISO"
(shape bidirectional) (shape bidirectional)
(at 39.37 143.51 180) (at 39.37 143.51 180)
(effects (effects
@@ -3388,7 +3388,7 @@
) )
(uuid "b01f227b-7e86-4d0e-83b2-5de764edeec9") (uuid "b01f227b-7e86-4d0e-83b2-5de764edeec9")
) )
(hierarchical_label "EXI_MISO" (hierarchical_label "EXI_MOSI"
(shape bidirectional) (shape bidirectional)
(at 39.37 140.97 180) (at 39.37 140.97 180)
(effects (effects
hardware/re-bba-rb/TODO.md
+19 -12
View File
@@ -6,18 +6,25 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
## Critical — must fix before (or with) next fab ## Critical — must fix before (or with) next fab
- [ ] **EXI DO/DI swapped at J3** (`exi.kicad_sch`). YAGCD SP1 naming is - [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
console-perspective: pin 6 `DO` = GC data **out** → adapter's MOSI YAGCD SP1 naming is console-perspective: pin 6 `DO` = GC data **out** →
*input*; pin 9 `DI` = GC data **in** ← adapter's MISO *output*. Board has adapter's MOSI *input*; pin 9 `DI` = GC data **in** ← adapter's MISO
J3.6 → EXI_MISO (FPGA output — bus contention with the GC driver) and *output* (verified via SD Gecko: MC pin 5 DO → SD CMD input; SD2SP2:
J3.9 → EXI_MOSI. Verified via SD Gecko (MC pin 5 DO → SD CMD input) and DO → OR gate → SD CMD). Fix applied as a pure rename/identity swap:
SD2SP2 (DO → OR gate → SD CMD). - [x] SP1 pin table in `docs/gc_bba_fpga_design.md` corrected (was the
- [ ] Fix the SP1 pin table in `docs/gc_bba_fpga_design.md` (§ SP1 root cause) + MISO-tristate note updated.
pinout, "DO (MISO) Adapter → GC" is backwards — root cause). - [x] Net names EXI_MOSI(_RAW) ↔ EXI_MISO(_RAW) swapped across
- [ ] Fix schematic labels (or PCB routing) so names match reality. `exi.kicad_sch`, `Fpga.kicad_sch`, root sheet, and the PCB — this
- [ ] Decide: keep current copper and swap in `synth.py` pin constraints also swaps the D2 (PUSB3AB6) channel assignments by name.
(both FPGA pins are plain IOBs: pin 3 = IOB_9b, pin 4 = IOB_8a), - [x] R21 (22 Ω) ↔ R25 (33 Ω) identities swapped between the two
or re-route. Existing boards are rescuable in constraints alone. positions so 33 Ω stays on the FPGA-driven MISO line and 22 Ω on
the MOSI input.
- [x] Verified: ERC 0, DRC 0 (incl. schematic parity 0), netlist:
J3.6(DO)→R21(22Ω)→**FPGA pin 4 (IOB_8a) = EXI_MOSI in**;
J3.9(DI)→R25(33Ω)→**FPGA pin 3 (IOB_9b) = EXI_MISO out**.
- [ ] Use this final pin map when writing the board PCF (see Broader
items): MOSI = pin 4, MISO = pin 3, CLK = 44 (G6), CS = 45,
INT = 46.
- [ ] **W5100S MDI termination network missing** (`ethernet.kicad_sch`). - [ ] **W5100S MDI termination network missing** (`ethernet.kicad_sch`).
Per WIZnet W5100S reference schematic: 49.9 Ω from each of Per WIZnet W5100S reference schematic: 49.9 Ω from each of
TXOP/TXON/RXIP/RXIN to a common node with 0.1 µF to GND, placed near the TXOP/TXON/RXIP/RXIN to a common node with 0.1 µF to GND, placed near the
hardware/re-bba-rb/exi.kicad_sch
+12 -12
View File
@@ -1423,7 +1423,7 @@
) )
(uuid "fd73b349-d700-4bfa-9b20-b662f3b5fa69") (uuid "fd73b349-d700-4bfa-9b20-b662f3b5fa69")
) )
(label "EXI_MISO_RAW" (label "EXI_MOSI_RAW"
(at 27.94 90.17 180) (at 27.94 90.17 180)
(effects (effects
(font (font
@@ -1433,7 +1433,7 @@
) )
(uuid "1673f89a-b196-4e3a-8b31-50ae5115685e") (uuid "1673f89a-b196-4e3a-8b31-50ae5115685e")
) )
(label "EXI_MOSI_RAW" (label "EXI_MISO_RAW"
(at 27.94 85.09 180) (at 27.94 85.09 180)
(effects (effects
(font (font
@@ -1463,7 +1463,7 @@
) )
(uuid "463748b5-0fc0-4757-8342-6383f5a7930f") (uuid "463748b5-0fc0-4757-8342-6383f5a7930f")
) )
(label "EXI_MISO_RAW" (label "EXI_MOSI_RAW"
(at 64.77 88.9 0) (at 64.77 88.9 0)
(effects (effects
(font (font
@@ -1493,7 +1493,7 @@
) )
(uuid "70f96782-2886-4b5b-94ad-95906cdd520c") (uuid "70f96782-2886-4b5b-94ad-95906cdd520c")
) )
(label "EXI_MOSI_RAW" (label "EXI_MISO_RAW"
(at 64.77 96.52 0) (at 64.77 96.52 0)
(effects (effects
(font (font
@@ -1586,7 +1586,7 @@
) )
(uuid "a7933167-c81c-41fc-a28b-3d624d2c6c3c") (uuid "a7933167-c81c-41fc-a28b-3d624d2c6c3c")
) )
(hierarchical_label "EXI_MISO" (hierarchical_label "EXI_MOSI"
(shape bidirectional) (shape bidirectional)
(at 74.93 88.9 0) (at 74.93 88.9 0)
(effects (effects
@@ -1608,7 +1608,7 @@
) )
(uuid "d8101c24-4fbe-49d0-a9c8-3adfc57b1ed6") (uuid "d8101c24-4fbe-49d0-a9c8-3adfc57b1ed6")
) )
(hierarchical_label "EXI_MOSI" (hierarchical_label "EXI_MISO"
(shape bidirectional) (shape bidirectional)
(at 74.93 96.52 0) (at 74.93 96.52 0)
(effects (effects
@@ -2056,7 +2056,7 @@
(dnp no) (dnp no)
(fields_autoplaced yes) (fields_autoplaced yes)
(uuid "329d834f-89a5-4c24-9ac5-f7fd739521d7") (uuid "329d834f-89a5-4c24-9ac5-f7fd739521d7")
(property "Reference" "R25" (property "Reference" "R21"
(at 68.58 82.55 90) (at 68.58 82.55 90)
(show_name no) (show_name no)
(do_not_autoplace no) (do_not_autoplace no)
@@ -2066,7 +2066,7 @@
) )
) )
) )
(property "Value" "33" (property "Value" "22"
(at 68.58 85.09 90) (at 68.58 85.09 90)
(show_name no) (show_name no)
(do_not_autoplace no) (do_not_autoplace no)
@@ -2151,7 +2151,7 @@
(instances (instances
(project "re-bba-rb" (project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/1b071f68-b4ea-469c-942f-de06380c9077" (path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/1b071f68-b4ea-469c-942f-de06380c9077"
(reference "R25") (reference "R21")
(unit 1) (unit 1)
) )
) )
@@ -2631,7 +2631,7 @@
(dnp no) (dnp no)
(fields_autoplaced yes) (fields_autoplaced yes)
(uuid "8bc64cda-903a-4cfc-b2c8-033616a6f51f") (uuid "8bc64cda-903a-4cfc-b2c8-033616a6f51f")
(property "Reference" "R21" (property "Reference" "R25"
(at 68.58 90.17 90) (at 68.58 90.17 90)
(show_name no) (show_name no)
(do_not_autoplace no) (do_not_autoplace no)
@@ -2641,7 +2641,7 @@
) )
) )
) )
(property "Value" "22" (property "Value" "33"
(at 68.58 92.71 90) (at 68.58 92.71 90)
(show_name no) (show_name no)
(do_not_autoplace no) (do_not_autoplace no)
@@ -2726,7 +2726,7 @@
(instances (instances
(project "re-bba-rb" (project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/1b071f68-b4ea-469c-942f-de06380c9077" (path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/1b071f68-b4ea-469c-942f-de06380c9077"
(reference "R21") (reference "R25")
(unit 1) (unit 1)
) )
) )
hardware/re-bba-rb/re-bba-rb.kicad_pcb
+48 -48
View File
@@ -4414,7 +4414,7 @@
(at 183.1675 66.92 180) (at 183.1675 66.92 180)
(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf)") (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf)")
(tags "resistor handsolder") (tags "resistor handsolder")
(property "Reference" "R25" (property "Reference" "R21"
(at 0.0175 2.39 0) (at 0.0175 2.39 0)
(layer "F.SilkS") (layer "F.SilkS")
(uuid "2411290f-1478-45df-b37f-76e549270bd9") (uuid "2411290f-1478-45df-b37f-76e549270bd9")
@@ -4425,7 +4425,7 @@
) )
) )
) )
(property "Value" "33" (property "Value" "22"
(at 0 1.17 0) (at 0 1.17 0)
(layer "F.Fab") (layer "F.Fab")
(uuid "9133d5ae-6fec-40fd-aa65-1edcc47bb7a2") (uuid "9133d5ae-6fec-40fd-aa65-1edcc47bb7a2")
@@ -4567,7 +4567,7 @@
(size 0.715 0.64) (size 0.715 0.64)
(layers "F.Cu" "F.Mask" "F.Paste") (layers "F.Cu" "F.Mask" "F.Paste")
(roundrect_rratio 0.25) (roundrect_rratio 0.25)
(net "/exi/EXI_MISO_RAW") (net "/exi/EXI_MOSI_RAW")
(pintype "passive") (pintype "passive")
(uuid "1b5a7353-4e45-40c7-9427-ee75341a965f") (uuid "1b5a7353-4e45-40c7-9427-ee75341a965f")
) )
@@ -4576,7 +4576,7 @@
(size 0.715 0.64) (size 0.715 0.64)
(layers "F.Cu" "F.Mask" "F.Paste") (layers "F.Cu" "F.Mask" "F.Paste")
(roundrect_rratio 0.25) (roundrect_rratio 0.25)
(net "/exi/EXI_MISO") (net "/exi/EXI_MOSI")
(pintype "passive") (pintype "passive")
(uuid "b0612162-d5e5-4ecd-95d1-dcd6c0fa59ef") (uuid "b0612162-d5e5-4ecd-95d1-dcd6c0fa59ef")
) )
@@ -4839,7 +4839,7 @@
(at -0.445 -0.75) (at -0.445 -0.75)
(size 0.74 0.26) (size 0.74 0.26)
(layers "F.Cu" "F.Paste") (layers "F.Cu" "F.Paste")
(net "/exi/EXI_MOSI_RAW") (net "/exi/EXI_MISO_RAW")
(pinfunction "CH1_1") (pinfunction "CH1_1")
(pintype "passive") (pintype "passive")
(uuid "6108fb47-fb3d-4991-b193-d699c4c13607") (uuid "6108fb47-fb3d-4991-b193-d699c4c13607")
@@ -4866,7 +4866,7 @@
(at -0.445 0.75) (at -0.445 0.75)
(size 0.74 0.26) (size 0.74 0.26)
(layers "F.Cu" "F.Paste") (layers "F.Cu" "F.Paste")
(net "/exi/EXI_MISO_RAW") (net "/exi/EXI_MOSI_RAW")
(pinfunction "CH3_4") (pinfunction "CH3_4")
(pintype "passive") (pintype "passive")
(uuid "b4db8299-4b09-40c0-9c0a-3cda0cede9f5") (uuid "b4db8299-4b09-40c0-9c0a-3cda0cede9f5")
@@ -5307,7 +5307,7 @@
(at 183.17 67.92 180) (at 183.17 67.92 180)
(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf)") (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf)")
(tags "resistor handsolder") (tags "resistor handsolder")
(property "Reference" "R21" (property "Reference" "R25"
(at -0.01 2.12 180) (at -0.01 2.12 180)
(layer "F.SilkS") (layer "F.SilkS")
(uuid "05025d92-fba4-4054-952c-ae0cdf4bb5a2") (uuid "05025d92-fba4-4054-952c-ae0cdf4bb5a2")
@@ -5318,7 +5318,7 @@
) )
) )
) )
(property "Value" "22" (property "Value" "33"
(at 0 1.17 0) (at 0 1.17 0)
(layer "F.Fab") (layer "F.Fab")
(uuid "d921d318-9c51-482a-b4f7-86c5dedaa5f5") (uuid "d921d318-9c51-482a-b4f7-86c5dedaa5f5")
@@ -5460,7 +5460,7 @@
(size 0.715 0.64) (size 0.715 0.64)
(layers "F.Cu" "F.Mask" "F.Paste") (layers "F.Cu" "F.Mask" "F.Paste")
(roundrect_rratio 0.25) (roundrect_rratio 0.25)
(net "/exi/EXI_MOSI_RAW") (net "/exi/EXI_MISO_RAW")
(pintype "passive") (pintype "passive")
(uuid "ca472b85-edcd-4a65-bab0-bf44738ec9fe") (uuid "ca472b85-edcd-4a65-bab0-bf44738ec9fe")
) )
@@ -5469,7 +5469,7 @@
(size 0.715 0.64) (size 0.715 0.64)
(layers "F.Cu" "F.Mask" "F.Paste") (layers "F.Cu" "F.Mask" "F.Paste")
(roundrect_rratio 0.25) (roundrect_rratio 0.25)
(net "/exi/EXI_MOSI") (net "/exi/EXI_MISO")
(pintype "passive") (pintype "passive")
(uuid "a555a28f-3636-4df4-a357-d1a04e31ff49") (uuid "a555a28f-3636-4df4-a357-d1a04e31ff49")
) )
@@ -15211,7 +15211,7 @@
(size 0.875 0.25) (size 0.875 0.25)
(layers "F.Cu" "F.Mask" "F.Paste") (layers "F.Cu" "F.Mask" "F.Paste")
(roundrect_rratio 0.25) (roundrect_rratio 0.25)
(net "/exi/EXI_MOSI") (net "/exi/EXI_MISO")
(pinfunction "IOB_9b_3") (pinfunction "IOB_9b_3")
(pintype "bidirectional") (pintype "bidirectional")
(uuid "69c14fe7-428d-4221-aa98-34ae8a2ed255") (uuid "69c14fe7-428d-4221-aa98-34ae8a2ed255")
@@ -15221,7 +15221,7 @@
(size 0.875 0.25) (size 0.875 0.25)
(layers "F.Cu" "F.Mask" "F.Paste") (layers "F.Cu" "F.Mask" "F.Paste")
(roundrect_rratio 0.25) (roundrect_rratio 0.25)
(net "/exi/EXI_MISO") (net "/exi/EXI_MOSI")
(pinfunction "IOB_8a_4") (pinfunction "IOB_8a_4")
(pintype "bidirectional") (pintype "bidirectional")
(uuid "020fbd3d-bde5-4bdb-9f25-429054419ae5") (uuid "020fbd3d-bde5-4bdb-9f25-429054419ae5")
@@ -17752,7 +17752,7 @@
(at 8 -4.2) (at 8 -4.2)
(size 1.5 2) (size 1.5 2)
(layers "F.Cu" "F.Mask" "F.Paste") (layers "F.Cu" "F.Mask" "F.Paste")
(net "/exi/EXI_MISO_RAW") (net "/exi/EXI_MOSI_RAW")
(pinfunction "DO_6") (pinfunction "DO_6")
(pintype "output") (pintype "output")
(uuid "81c570a3-a82d-4ba6-b65e-766e7a9df6fd") (uuid "81c570a3-a82d-4ba6-b65e-766e7a9df6fd")
@@ -17763,7 +17763,7 @@
(drill 1) (drill 1)
(layers "*.Cu" "F.Mask") (layers "*.Cu" "F.Mask")
(remove_unused_layers no) (remove_unused_layers no)
(net "/exi/EXI_MISO_RAW") (net "/exi/EXI_MOSI_RAW")
(pinfunction "DO_6") (pinfunction "DO_6")
(pintype "output") (pintype "output")
(thermal_bridge_angle 90) (thermal_bridge_angle 90)
@@ -17817,7 +17817,7 @@
(drill 1) (drill 1)
(layers "*.Cu" "F.Mask") (layers "*.Cu" "F.Mask")
(remove_unused_layers no) (remove_unused_layers no)
(net "/exi/EXI_MOSI_RAW") (net "/exi/EXI_MISO_RAW")
(pinfunction "DI_9") (pinfunction "DI_9")
(pintype "input") (pintype "input")
(thermal_bridge_angle 90) (thermal_bridge_angle 90)
@@ -17827,7 +17827,7 @@
(at 5 -0.8) (at 5 -0.8)
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