Fix EXI DO/DI swap: rename nets + swap damping resistors, no copper changes

SP1 DO/DI naming is console-perspective (verified against SD Gecko and SD2SP2 wiring): pin 6 DO = GC data out = adapter MOSI input, pin 9 DI = GC data in = adapter MISO output. The design doc's SP1 table had the roles reversed and the schematic followed it, putting the FPGA's MISO driver on the GC-driven DO line (bus contention). Fix keeps all PCB routing identical: - Swap net names EXI_MOSI(_RAW) <-> EXI_MISO(_RAW) across exi/Fpga/root sheets and the PCB (also renames the D2 PUSB3AB6 channel assignments). - Swap R21 (22R) <-> R25 (33R) identities between the two footprint positions so 33R stays on the FPGA-driven MISO line, 22R on the MOSI input. - Correct the SP1 pin table + MISO-tristate note in docs/gc_bba_fpga_design.md (root cause). Resulting board pin map (for the future board PCF): EXI_MOSI = FPGA pin 4 (IOB_8a, input), EXI_MISO = pin 3 (IOB_9b, output). Verified: ERC 0, DRC 0 errors with schematic parity 0, netlist shows J3.6(DO)->R21->pin 4 and J3.9(DI)->R25->pin 3. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-18 12:36:41 +00:00
parent 4704dfbb36
commit fe96876a80
7 changed files with 94 additions and 86 deletions
@@ -256,11 +256,11 @@ before ordering the interposer PCB; not part of the FPGA build.
 `hardware/re-bba-rb/` — the actual adapter PCB (FT2232H + iCE40UP5K + W5100S,
 powered from SP1 12 V via buck). **Open findings from the 2026-07-17 hardware
 review live in `hardware/re-bba-rb/TODO.md`** — read it before editing the
-schematics, ordering boards, or writing the board PCF. Highlights: EXI DO/DI are
-swapped vs the (incorrect) SP1 table in `docs/gc_bba_fpga_design.md` (DO = GC→
-adapter = MOSI); the W5100S MDI 49.9 Ω termination network is missing; the FTDI
-EEPROM needs its 2.2 k/10 k resistors; stock iceprog doesn't match the FTDI pin
-mapping.
+schematics, ordering boards, or writing the board PCF. Highlights: the W5100S
+MDI 49.9 Ω termination network is missing; the FTDI EEPROM needs its 2.2 k/10 k
+resistors; stock iceprog doesn't match the FTDI pin mapping. (The EXI DO/DI
+swap found in the review is FIXED — SP1 naming is console-perspective, DO = GC→
+adapter = MOSI; board pin map: EXI_MOSI = FPGA pin 4, EXI_MISO = pin 3.)

 ---

@@ -146,10 +146,10 @@ pin 1 is also on the left — numbering does not mirror.
 | 3 | INT | Adapter → GC | Active-low interrupt to GC CPU. Assert when IR & IMR != 0. |
 | 4 | CLK | GC → Adapter | SPI clock, up to 32 MHz, idles HIGH (Mode 3) |
 | 5 | 12V | — | 12 V supply from GC. **Do not connect to FPGA I/O.** Leave unconnected or route to a test point only. |
-| 6 | DO (MISO) | Adapter → GC | Serial data out: adapter drives, GC samples |
+| 6 | DO (MOSI) | GC → Adapter | Serial data out **of the GC** (console-perspective name): GC drives, adapter samples. Verified against SD Gecko/SD2SP2 wiring — do not swap. |
 | 7 | 3.3V | — | 3.3 V supply (~200 mA available combined with pin 8) |
 | 8 | 3.3V | — | 3.3 V supply (parallel with pin 7) |
-| 9 | DI (MOSI) | GC → Adapter | Serial data in: GC drives, adapter samples |
+| 9 | DI (MISO) | Adapter → GC | Serial data in **to the GC** (console-perspective name): adapter drives, GC samples |
 | 10 | CS | GC → Adapter | Chip select, active low. Delineates each transaction. |
 | 11 | GND | — | Signal ground |
 | 12 | GND | — | Signal ground |
@@ -1296,7 +1296,8 @@ with other EXI device implementations without parameterising CPOL/CPHA.

 ### MISO tristate

-On real hardware, MISO (DO) is tristated when CS is deasserted. Other EXI
+On real hardware, MISO (SP1 pin 9, "DI" in console-perspective naming) is
+tristated when CS is deasserted. Other EXI
 devices on the same bus would otherwise conflict. On this FPGA implementation,
 drive MISO high (not tristated) when CS is deasserted. The iCE40UP5K does
 not easily support pin tristate from user logic — drive high is safe because
@@ -3135,7 +3135,7 @@
 		)
 		(uuid "1263a374-a091-46fb-835b-d4113957a468")
 	)
-	(hierarchical_label "EXI_MOSI"
+	(hierarchical_label "EXI_MISO"
 		(shape bidirectional)
 		(at 39.37 143.51 180)
 		(effects
@@ -3388,7 +3388,7 @@
 		)
 		(uuid "b01f227b-7e86-4d0e-83b2-5de764edeec9")
 	)
-	(hierarchical_label "EXI_MISO"
+	(hierarchical_label "EXI_MOSI"
 		(shape bidirectional)
 		(at 39.37 140.97 180)
 		(effects
@@ -6,18 +6,25 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.

 ## Critical — must fix before (or with) next fab

- [ ] **EXI DO/DI swapped at J3** (`exi.kicad_sch`). YAGCD SP1 naming is
-      console-perspective: pin 6 `DO` = GC data **out** → adapter's MOSI
-      *input*; pin 9 `DI` = GC data **in** ← adapter's MISO *output*. Board has
-      J3.6 → EXI_MISO (FPGA output — bus contention with the GC driver) and
-      J3.9 → EXI_MOSI. Verified via SD Gecko (MC pin 5 DO → SD CMD input) and
-      SD2SP2 (DO → OR gate → SD CMD).
-      - [ ] Fix the SP1 pin table in `docs/gc_bba_fpga_design.md` (§ SP1
-            pinout, "DO (MISO) Adapter → GC" is backwards — root cause).
-      - [ ] Fix schematic labels (or PCB routing) so names match reality.
-      - [ ] Decide: keep current copper and swap in `synth.py` pin constraints
-            (both FPGA pins are plain IOBs: pin 3 = IOB_9b, pin 4 = IOB_8a),
-            or re-route. Existing boards are rescuable in constraints alone.
+- [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
+      YAGCD SP1 naming is console-perspective: pin 6 `DO` = GC data **out** →
+      adapter's MOSI *input*; pin 9 `DI` = GC data **in** ← adapter's MISO
+      *output* (verified via SD Gecko: MC pin 5 DO → SD CMD input; SD2SP2:
+      DO → OR gate → SD CMD). Fix applied as a pure rename/identity swap:
+      - [x] SP1 pin table in `docs/gc_bba_fpga_design.md` corrected (was the
+            root cause) + MISO-tristate note updated.
+      - [x] Net names EXI_MOSI(_RAW) ↔ EXI_MISO(_RAW) swapped across
+            `exi.kicad_sch`, `Fpga.kicad_sch`, root sheet, and the PCB — this
+            also swaps the D2 (PUSB3AB6) channel assignments by name.
+      - [x] R21 (22 Ω) ↔ R25 (33 Ω) identities swapped between the two
+            positions so 33 Ω stays on the FPGA-driven MISO line and 22 Ω on
+            the MOSI input.
+      - [x] Verified: ERC 0, DRC 0 (incl. schematic parity 0), netlist:
+            J3.6(DO)→R21(22Ω)→**FPGA pin 4 (IOB_8a) = EXI_MOSI in**;
+            J3.9(DI)→R25(33Ω)→**FPGA pin 3 (IOB_9b) = EXI_MISO out**.
+      - [ ] Use this final pin map when writing the board PCF (see Broader
+            items): MOSI = pin 4, MISO = pin 3, CLK = 44 (G6), CS = 45,
+            INT = 46.
 - [ ] **W5100S MDI termination network missing** (`ethernet.kicad_sch`).
      Per WIZnet W5100S reference schematic: 49.9 Ω from each of
      TXOP/TXON/RXIP/RXIN to a common node with 0.1 µF to GND, placed near the
@@ -1423,7 +1423,7 @@
 		)
 		(uuid "fd73b349-d700-4bfa-9b20-b662f3b5fa69")
 	)
-	(label "EXI_MISO_RAW"
+	(label "EXI_MOSI_RAW"
 		(at 27.94 90.17 180)
 		(effects
 			(font
@@ -1433,7 +1433,7 @@
 		)
 		(uuid "1673f89a-b196-4e3a-8b31-50ae5115685e")
 	)
-	(label "EXI_MOSI_RAW"
+	(label "EXI_MISO_RAW"
 		(at 27.94 85.09 180)
 		(effects
 			(font
@@ -1463,7 +1463,7 @@
 		)
 		(uuid "463748b5-0fc0-4757-8342-6383f5a7930f")
 	)
-	(label "EXI_MISO_RAW"
+	(label "EXI_MOSI_RAW"
 		(at 64.77 88.9 0)
 		(effects
 			(font
@@ -1493,7 +1493,7 @@
 		)
 		(uuid "70f96782-2886-4b5b-94ad-95906cdd520c")
 	)
-	(label "EXI_MOSI_RAW"
+	(label "EXI_MISO_RAW"
 		(at 64.77 96.52 0)
 		(effects
 			(font
@@ -1586,7 +1586,7 @@
 		)
 		(uuid "a7933167-c81c-41fc-a28b-3d624d2c6c3c")
 	)
-	(hierarchical_label "EXI_MISO"
+	(hierarchical_label "EXI_MOSI"
 		(shape bidirectional)
 		(at 74.93 88.9 0)
 		(effects
@@ -1608,7 +1608,7 @@
 		)
 		(uuid "d8101c24-4fbe-49d0-a9c8-3adfc57b1ed6")
 	)
-	(hierarchical_label "EXI_MOSI"
+	(hierarchical_label "EXI_MISO"
 		(shape bidirectional)
 		(at 74.93 96.52 0)
 		(effects
@@ -2056,7 +2056,7 @@
 		(dnp no)
 		(fields_autoplaced yes)
 		(uuid "329d834f-89a5-4c24-9ac5-f7fd739521d7")
-		(property "Reference" "R25"
+		(property "Reference" "R21"
 			(at 68.58 82.55 90)
 			(show_name no)
 			(do_not_autoplace no)
@@ -2066,7 +2066,7 @@
 				)
 			)
 		)
-		(property "Value" "33"
+		(property "Value" "22"
 			(at 68.58 85.09 90)
 			(show_name no)
 			(do_not_autoplace no)
@@ -2151,7 +2151,7 @@
 		(instances
 			(project "re-bba-rb"
 				(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/1b071f68-b4ea-469c-942f-de06380c9077"
-					(reference "R25")
+					(reference "R21")
 					(unit 1)
 				)
 			)
@@ -2631,7 +2631,7 @@
 		(dnp no)
 		(fields_autoplaced yes)
 		(uuid "8bc64cda-903a-4cfc-b2c8-033616a6f51f")
-		(property "Reference" "R21"
+		(property "Reference" "R25"
 			(at 68.58 90.17 90)
 			(show_name no)
 			(do_not_autoplace no)
@@ -2641,7 +2641,7 @@
 				)
 			)
 		)
-		(property "Value" "22"
+		(property "Value" "33"
 			(at 68.58 92.71 90)
 			(show_name no)
 			(do_not_autoplace no)
@@ -2726,7 +2726,7 @@
 		(instances
 			(project "re-bba-rb"
 				(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/1b071f68-b4ea-469c-942f-de06380c9077"
-					(reference "R21")
+					(reference "R25")
 					(unit 1)
 				)
 			)
@@ -4414,7 +4414,7 @@
 		(at 183.1675 66.92 180)
 		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf)")
 		(tags "resistor handsolder")
-		(property "Reference" "R25"
+		(property "Reference" "R21"
 			(at 0.0175 2.39 0)
 			(layer "F.SilkS")
 			(uuid "2411290f-1478-45df-b37f-76e549270bd9")
@@ -4425,7 +4425,7 @@
 				)
 			)
 		)
-		(property "Value" "33"
+		(property "Value" "22"
 			(at 0 1.17 0)
 			(layer "F.Fab")
 			(uuid "9133d5ae-6fec-40fd-aa65-1edcc47bb7a2")
@@ -4567,7 +4567,7 @@
 			(size 0.715 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net "/exi/EXI_MISO_RAW")
+			(net "/exi/EXI_MOSI_RAW")
 			(pintype "passive")
 			(uuid "1b5a7353-4e45-40c7-9427-ee75341a965f")
 		)
@@ -4576,7 +4576,7 @@
 			(size 0.715 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net "/exi/EXI_MISO")
+			(net "/exi/EXI_MOSI")
 			(pintype "passive")
 			(uuid "b0612162-d5e5-4ecd-95d1-dcd6c0fa59ef")
 		)
@@ -4839,7 +4839,7 @@
 			(at -0.445 -0.75)
 			(size 0.74 0.26)
 			(layers "F.Cu" "F.Paste")
-			(net "/exi/EXI_MOSI_RAW")
+			(net "/exi/EXI_MISO_RAW")
 			(pinfunction "CH1_1")
 			(pintype "passive")
 			(uuid "6108fb47-fb3d-4991-b193-d699c4c13607")
@@ -4866,7 +4866,7 @@
 			(at -0.445 0.75)
 			(size 0.74 0.26)
 			(layers "F.Cu" "F.Paste")
-			(net "/exi/EXI_MISO_RAW")
+			(net "/exi/EXI_MOSI_RAW")
 			(pinfunction "CH3_4")
 			(pintype "passive")
 			(uuid "b4db8299-4b09-40c0-9c0a-3cda0cede9f5")
@@ -5307,7 +5307,7 @@
 		(at 183.17 67.92 180)
 		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf)")
 		(tags "resistor handsolder")
-		(property "Reference" "R21"
+		(property "Reference" "R25"
 			(at -0.01 2.12 180)
 			(layer "F.SilkS")
 			(uuid "05025d92-fba4-4054-952c-ae0cdf4bb5a2")
@@ -5318,7 +5318,7 @@
 				)
 			)
 		)
-		(property "Value" "22"
+		(property "Value" "33"
 			(at 0 1.17 0)
 			(layer "F.Fab")
 			(uuid "d921d318-9c51-482a-b4f7-86c5dedaa5f5")
@@ -5460,7 +5460,7 @@
 			(size 0.715 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net "/exi/EXI_MOSI_RAW")
+			(net "/exi/EXI_MISO_RAW")
 			(pintype "passive")
 			(uuid "ca472b85-edcd-4a65-bab0-bf44738ec9fe")
 		)
@@ -5469,7 +5469,7 @@
 			(size 0.715 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net "/exi/EXI_MOSI")
+			(net "/exi/EXI_MISO")
 			(pintype "passive")
 			(uuid "a555a28f-3636-4df4-a357-d1a04e31ff49")
 		)
@@ -15211,7 +15211,7 @@
 			(size 0.875 0.25)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net "/exi/EXI_MOSI")
+			(net "/exi/EXI_MISO")
 			(pinfunction "IOB_9b_3")
 			(pintype "bidirectional")
 			(uuid "69c14fe7-428d-4221-aa98-34ae8a2ed255")
@@ -15221,7 +15221,7 @@
 			(size 0.875 0.25)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net "/exi/EXI_MISO")
+			(net "/exi/EXI_MOSI")
 			(pinfunction "IOB_8a_4")
 			(pintype "bidirectional")
 			(uuid "020fbd3d-bde5-4bdb-9f25-429054419ae5")
@@ -17752,7 +17752,7 @@
 			(at 8 -4.2)
 			(size 1.5 2)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/exi/EXI_MISO_RAW")
+			(net "/exi/EXI_MOSI_RAW")
 			(pinfunction "DO_6")
 			(pintype "output")
 			(uuid "81c570a3-a82d-4ba6-b65e-766e7a9df6fd")
@@ -17763,7 +17763,7 @@
 			(drill 1)
 			(layers "*.Cu" "F.Mask")
 			(remove_unused_layers no)
-			(net "/exi/EXI_MISO_RAW")
+			(net "/exi/EXI_MOSI_RAW")
 			(pinfunction "DO_6")
 			(pintype "output")
 			(thermal_bridge_angle 90)
@@ -17817,7 +17817,7 @@
 			(drill 1)
 			(layers "*.Cu" "F.Mask")
 			(remove_unused_layers no)
-			(net "/exi/EXI_MOSI_RAW")
+			(net "/exi/EXI_MISO_RAW")
 			(pinfunction "DI_9")
 			(pintype "input")
 			(thermal_bridge_angle 90)
@@ -17827,7 +17827,7 @@
 			(at 5 -0.8)
 			(size 1.5 2)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/exi/EXI_MOSI_RAW")
+			(net "/exi/EXI_MISO_RAW")
 			(pinfunction "DI_9")
 			(pintype "input")
 			(uuid "773ce9d0-56f5-4743-8ff5-55c7cf07bf1a")
@@ -33393,7 +33393,7 @@
 		(end 187.5 63.25)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "02e1c0d6-0a9b-4d2b-a944-c576cc0e8395")
 	)
 	(segment
@@ -33401,7 +33401,7 @@
 		(end 197.85 53.28)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "04c9ca2c-74d0-4d5f-bc38-984e0e0a80c5")
 	)
 	(segment
@@ -33409,7 +33409,7 @@
 		(end 196.5 51.93)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "3e8a3a86-3929-4467-882d-052d0a2ed63a")
 	)
 	(segment
@@ -33417,7 +33417,7 @@
 		(end 183.83 66.92)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "43614f5f-d489-4157-a59c-b0eea267998d")
 	)
 	(segment
@@ -33425,7 +33425,7 @@
 		(end 196.73 51.7)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "b195276b-353c-4883-8330-abd312c103d8")
 	)
 	(segment
@@ -33433,7 +33433,7 @@
 		(end 196.5 51.93)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "b2fd5d61-4e18-42cd-b044-15f024ff82b8")
 	)
 	(segment
@@ -33441,7 +33441,7 @@
 		(end 188 52)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "c13a9aa0-bf14-45da-83c0-55e1b75b7116")
 	)
 	(segment
@@ -33449,7 +33449,7 @@
 		(end 187.5 52.5)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "e0114465-137b-414b-aed1-dc4d8d8ac849")
 	)
 	(via
@@ -33457,7 +33457,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "37d66f40-6d91-44ac-be0a-0aa4a39bd049")
 	)
 	(via
@@ -33465,7 +33465,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "a84d35ab-2f68-4279-9b59-9ffb6c17c7bf")
 	)
 	(segment
@@ -33473,7 +33473,7 @@
 		(end 196.43 52)
 		(width 0.2)
 		(layer "B.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "32d8ca95-ee25-4085-9c1e-c52dd084270b")
 	)
 	(segment
@@ -33481,7 +33481,7 @@
 		(end 196.5 51.93)
 		(width 0.2)
 		(layer "B.Cu")
-		(net "/exi/EXI_MISO_RAW")
+		(net "/exi/EXI_MOSI_RAW")
 		(uuid "e522e8c8-0ac1-48e5-8c3c-fd8766e1c3a4")
 	)
 	(segment
@@ -33489,7 +33489,7 @@
 		(end 173.72 66.92)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO")
+		(net "/exi/EXI_MOSI")
 		(uuid "3a91dd81-8154-4b53-92df-899ae0342f4c")
 	)
 	(segment
@@ -33497,7 +33497,7 @@
 		(end 173.34 67.3)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO")
+		(net "/exi/EXI_MOSI")
 		(uuid "4b3cdf8b-248c-40f3-8818-5b2ae3bb9955")
 	)
 	(segment
@@ -33505,7 +33505,7 @@
 		(end 171.28 67.3)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO")
+		(net "/exi/EXI_MOSI")
 		(uuid "7d4c303c-e577-4ab7-996d-ca098b355255")
 	)
 	(segment
@@ -33513,7 +33513,7 @@
 		(end 171.13 67.15)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO")
+		(net "/exi/EXI_MOSI")
 		(uuid "a8cb01e6-6242-4724-b8d8-56726df9ba17")
 	)
 	(segment
@@ -33521,7 +33521,7 @@
 		(end 170.34 67.15)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MISO")
+		(net "/exi/EXI_MOSI")
 		(uuid "c751749e-f969-4573-b17e-1d07e5b85c00")
 	)
 	(segment
@@ -33529,7 +33529,7 @@
 		(end 191.22 60.44)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "004c08b8-56e4-466c-bb1a-36bf4fb8b1a7")
 	)
 	(segment
@@ -33537,7 +33537,7 @@
 		(end 190.07 54.907818)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "056ec60b-6fe0-4052-8644-636380a489b3")
 	)
 	(segment
@@ -33545,7 +33545,7 @@
 		(end 194.85 59.35)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "14125abe-ac1f-46a7-a7b3-3c2980b0bbd7")
 	)
 	(segment
@@ -33553,7 +33553,7 @@
 		(end 188 63.6875)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "1509c7e0-d5a0-48fd-9fec-eade2ea70691")
 	)
 	(segment
@@ -33561,7 +33561,7 @@
 		(end 193.76 60.44)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "2034dbd8-32ff-4ae8-87b1-b6f5d046b39c")
 	)
 	(segment
@@ -33569,7 +33569,7 @@
 		(end 188 53)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "5e6ab5da-8a33-428c-95ba-9b1a6b43d3be")
 	)
 	(segment
@@ -33577,7 +33577,7 @@
 		(end 193.988909 50.988909)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "8a82ac0a-2f05-4402-acd1-e00b4d8182a3")
 	)
 	(segment
@@ -33585,7 +33585,7 @@
 		(end 190.011091 50.988909)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "9647430f-101b-40fc-8276-b373866509b1")
 	)
 	(segment
@@ -33593,7 +33593,7 @@
 		(end 194.85 59.1)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "a72206c4-bce4-4847-9beb-658d236185b5")
 	)
 	(segment
@@ -33601,7 +33601,7 @@
 		(end 190.07 59.29)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "d13c2368-9a72-4261-bb1b-dbe987899e16")
 	)
 	(segment
@@ -33609,7 +33609,7 @@
 		(end 193.988909 50.988909)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "d6c84969-6d5b-4596-b54a-ef1b07c61b0b")
 	)
 	(segment
@@ -33617,7 +33617,7 @@
 		(end 194.777818 50.2)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI_RAW")
+		(net "/exi/EXI_MISO_RAW")
 		(uuid "e4d62c50-8548-47ab-82c6-22a0438c8d02")
 	)
 	(segment
@@ -34417,7 +34417,7 @@
 		(end 173.65 67.92)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI")
+		(net "/exi/EXI_MISO")
 		(uuid "28662ed1-c7ad-44c1-8d88-806dbb5e4f37")
 	)
 	(segment
@@ -34425,7 +34425,7 @@
 		(end 173.38 67.65)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI")
+		(net "/exi/EXI_MISO")
 		(uuid "831e39c2-caa8-4ee4-bbfb-53104cf201f8")
 	)
 	(segment
@@ -34433,7 +34433,7 @@
 		(end 173.38 67.65)
 		(width 0.2)
 		(layer "F.Cu")
-		(net "/exi/EXI_MOSI")
+		(net "/exi/EXI_MISO")
 		(uuid "c2a10804-ce60-4903-809a-469e58979f51")
 	)
 	(segment
@@ -611,7 +611,7 @@
 				(justify right)
 			)
 		)
-		(pin "EXI_MISO" bidirectional
+		(pin "EXI_MOSI" bidirectional
 			(at 55.88 81.28 0)
 			(uuid "0dcf5cdd-0199-4cd1-9b91-0a62b49304f2")
 			(effects
@@ -621,7 +621,7 @@
 				(justify right)
 			)
 		)
-		(pin "EXI_MOSI" bidirectional
+		(pin "EXI_MISO" bidirectional
 			(at 55.88 83.82 0)
 			(uuid "4fb4e7d3-76e2-41e1-8083-ce5f6cb6c061")
 			(effects
@@ -1199,7 +1199,7 @@
 				(justify left)
 			)
 		)
-		(pin "EXI_MISO" bidirectional
+		(pin "EXI_MOSI" bidirectional
 			(at 104.14 81.28 180)
 			(uuid "0979d259-b2b8-44f3-968b-ffbc5fbcbaaa")
 			(effects
@@ -1209,7 +1209,7 @@
 				(justify left)
 			)
 		)
-		(pin "EXI_MOSI" bidirectional
+		(pin "EXI_MISO" bidirectional
 			(at 104.14 83.82 180)
 			(uuid "5f9986c7-d126-40ae-8e10-3ed93f86746d")
 			(effects