Fixes the GC/USB power led handover

Added Silkscreen labels
Adds last Todo item, fixes CPL and rotations.
2026-09-02 21:34:17 +02:00 · 2026-09-02 21:14:06 +02:00 · 2026-09-02 21:00:08 +02:00 · 2026-08-28 17:17:54 +02:00 · 2026-08-28 10:29:41 +02:00 · 2026-08-22 18:57:52 +00:00
28 changed files with 57852 additions and 25519 deletions
@@ -0,0 +1,135 @@
+---
+name: flash-re-bba-rb
+description: Use when flashing the re-bba-rb board (GC BBA FPGA replacement) — programming the iCE40UP5K bitstream with iceprog from inside the devcontainer (native-Linux or WSL2 host USB passthrough). Covers USB prerequisites, best-seed bitstream selection, sudo/libusb access. WARNING: on V1 the FT2232H EEPROM (U7 93LC46B) is undersized and writing the product string SOFT-BRICKS enumeration — the skill documents why not to, and the CLK-to-GND recovery.
+---
+
+# Flashing the re-bba-rb board
+
+The board is FT2232H (USB) → iCE40UP5K (FPGA) + W5100S (ethernet). Two flashable
+targets, done **in this order**:
+
+1. **FPGA bitstream** via `iceprog` (MPSSE on FT2232H channel A) — the functional
+   flash. Do this first; it works with a blank EEPROM.
+2. **FT2232H EEPROM** product string via `pyftdi` — cosmetic ("re-BBA-rb" instead
+   of "Dual RS232-HS"). Optional, do it only after the bitstream is proven.
+
+Both need USB access to the FT2232H (VID:PID `0403:6010`) from inside the
+container. The `vscode` user reaches the root-owned `/dev/bus/usb` nodes via
+passwordless `sudo`.
+
+## Prerequisites (once per session)
+
+1. **Container built with USB access.** `.devcontainer/` must have `--privileged`,
+   the `/dev/bus/usb` bind mount, `sudo`, `libusb-1.0-0`, `libftdi1-2`, and
+   `pyftdi`. If `.devcontainer/` was just edited, the user must **rebuild the
+   container** — those changes are baked at build/create time.
+2. **Device attached to WSL2.** On the Windows host, as Administrator:
+   `.devcontainer/attach-icebreaker.ps1` (wraps `usbipd attach`). Attach before
+   or after container start — the bind mount is live, so a later attach still
+   appears.
+3. **Confirm the device is visible from inside the container:**
+   ```bash
+   ls /dev/bus/usb/*/*                      # nodes must exist
+   sudo /opt/venv/bin/python -c "import usb.core,usb.backend.libusb1 as b; \
+     print(usb.core.find(idVendor=0x0403, idProduct=0x6010, backend=b.get_backend()))"
+   ```
+   A non-`None` device object means libusb can see it. If `/dev/bus/usb` is empty,
+   the device is not attached (fix on the Windows side) — see Troubleshooting.
+
+## Step 1 — Flash the FPGA bitstream
+
+The design's `capture` domain (54 MHz) closes on only a **minority of seeds** —
+always sweep and flash the **best passing** seed, never the default seed-1 build.
+
+```bash
+# Build all 8 seeds (from workspace root). Prints the best passing seed + path.
+python -m exi_bba.synth --seeds 8
+```
+Note the reported best seed, e.g. `Best seed: 4  ... build/seed4/top.bin`. (As of
+the last build: **seed 4, `build/seed4/top.bin`, capture 58.36 MHz**, 4/8 pass.
+`build/` is on the host bind mount, so it survives container rebuilds.)
+
+Flash it (SRAM-less part → `iceprog` writes the SPI flash; the FPGA boots from
+it):
+```bash
+sudo iceprog build/seed4/top.bin        # substitute the reported best-seed path
+```
+Expect `iceprog` to detect the FTDI, erase, write, and **verify OK**. If it says
+"Can't find iCE FTDI USB device", the USB passthrough is not working — see
+Troubleshooting. After a successful flash, power-cycle / re-plug to boot the new
+image.
+
+`ICEPROG=/path/to/iceprog` overrides the binary if needed; the container's is on
+`PATH`.
+
+## Step 2 — FT2232H EEPROM product string — ⚠️ DO NOT DO THIS ON V1
+
+**On the re-bba-rb V1 board, writing the EEPROM product string SOFT-BRICKS the
+FT2232H.** U7 is a 93LC46B (128 B), too small for the FT2232H (which needs a
+93LC56B / 256 B). A string write lands a partial, checksum-valid-but-garbage
+config; the FT2232H reads it at power-up and **fails USB enumeration entirely —
+dead silent, no `dmesg` attach.** It does NOT fall back to ROM defaults (only a
+BLANK / checksum-invalid EEPROM does). Confirmed on hardware 2026-08-22.
+
+`flash_ftdi_eeprom.py` **detects the mirrored/undersized chip and refuses the
+write** — leave it that way. There is no way to program the string on V1; it
+needs a 93LC56B at U7 (a future rev). The board is fully functional without it:
+it enumerates on ROM defaults (`Dual RS232-HS`, `0403:6010`) and iceprog + the
+channel-B UART work normally.
+
+### Recovery — if U7 ever gets a bad config written (soft-brick)
+
+Symptom: the FT2232H disappears from USB completely (no `dmesg` on plug) even
+though it's powered (3.3 V on VCC/VPHY/RESET#/DP all present). Fix — the classic
+FTDI EEPROM recovery, done on the V1 unit and confirmed working:
+
+1. **Power the board on with U7's CLK pin shorted to GND.** This corrupts the
+   EEPROM read so the FT2232H can't load the bad config → it enumerates on ROM
+   defaults (`0403:6010`).
+2. Release the short and immediately blank U7:
+   ```bash
+   sudo /opt/venv/bin/python hardware/re-bba-rb/flash_ftdi_eeprom.py --erase --commit
+   ```
+   (On the mirrored chip pyftdi's 256-byte verify trips even though the 0xFF
+   writes land — the script loops and checks actual content, so ignore the
+   per-attempt verify warnings; it reports "fully blank" when done.)
+
+To restore a saved backup instead, write `eeprom-backup.bin` back as a raw image.
+
+## Troubleshooting
+
+- **`/dev/bus/usb` empty / device object is `None`** → the FT2232H isn't on the
+  host bus (the container's `/dev/bus/usb` mirrors the host live). On a **native
+  Linux host** (e.g. Arch — Docker directly): `lsusb | grep 0403` on the host; if
+  missing, re-plug the cable. On a **Windows/WSL2 host**: run
+  `.devcontainer/attach-icebreaker.ps1` (admin) and check `usbipd list` shows it
+  `Attached`.
+- **Powered but totally silent on plug (no `dmesg` attach at all)** → most likely
+  a soft-bricked FT2232H EEPROM (see Step 2 recovery) if the EEPROM was ever
+  written; otherwise a severed USB power/data via from the board repair. A blank
+  EEPROM does NOT cause this — a *partial* write does.
+- **`Permission denied` / `LIBUSB_ERROR_ACCESS`** → run the command under `sudo`
+  (the nodes are root-owned). Both `iceprog` and the pyftdi script need it.
+- **`iceprog` can't find the device but `pyftdi` sees it (or vice-versa)** → a
+  kernel driver (`ftdi_sio`) may hold an interface. `iceprog`/`pyftdi` detach it
+  automatically under sudo; if stuck, `sudo modprobe -r ftdi_sio` (or re-attach
+  the device) and retry.
+- **`iceprog` verify fails / flakey** → the drilled-out-via repair on this V1
+  unit may have damaged a flash/CDONE/CRESET trace; check continuity of the SPI
+  flash lines and CRESET_B/CDONE to the FPGA before assuming gateware fault.
+- **FPGA boots but the GC won't enumerate the BBA** → this is a *timing* seed
+  issue, not a flash issue. Re-flash the reported **best passing** seed (the
+  capture domain fails on ~half of seeds). See CLAUDE.md "Current Implementation
+  State".
+
+## Guardrails
+
+- **Do NOT program the EEPROM string on V1 — it soft-bricks the FT2232H** (U7 is
+  an undersized 93LC46B; see Step 2). The script refuses by design; do not
+  `--force` it. Recovery is CLK-to-GND at boot + `--erase`.
+- **Never change VID/PID** in the EEPROM — `iceprog` and D2XX look for
+  `0403:6010`. The script/conf keep it; don't override.
+- **Always flash the swept best-seed** `.bin`, never a no-`--seeds` seed-1 build
+  (capture timing fails on it).
+- A **blank** EEPROM is the correct, working state on V1; only a *partial* write
+  is dangerous.
@@ -4,18 +4,25 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
    ca-certificates \
    git \
    git-lfs \
+    sudo \
    python3 \
    python3-venv \
    python3-pip \
    yosys \
    nextpnr-ice40 \
    fpga-icestorm \
+    libusb-1.0-0 \
+    libftdi1-2 \
+    tshark \
    nodejs npm \
    graphviz \
    poppler-utils \
    kicad \
    kicad-libraries \
    && rm -rf /var/lib/apt/lists/*
+# libusb-1.0-0 + libftdi1-2: USB backend for `iceprog` (FPGA flash) and `pyftdi`
+# (FT2232H EEPROM).  sudo: the /dev/bus/usb nodes are root-owned, so the vscode
+# user flashes via `sudo` (NOPASSWD, configured below).

 # Debian marks the system Python as externally-managed (PEP 668), so install
 # project deps into a venv. /opt/venv is first on PATH, so `python`/`pip` resolve
@@ -24,12 +31,25 @@ ENV VIRTUAL_ENV=/opt/venv
 RUN python3 -m venv "$VIRTUAL_ENV"
 ENV PATH="$VIRTUAL_ENV/bin:$PATH"

+# ENV PATH alone is not enough: Debian's /etc/profile REsets PATH unconditionally,
+# so any *login* shell (VS Code's integrated terminal, `su - vscode`, ssh) drops
+# /opt/venv/bin and then `python` does not exist at all (slim has only python3).
+# Re-prepend the venv for login shells so the documented `python -m exi_bba.synth`
+# works everywhere.
+RUN printf 'PATH="%s/bin:$PATH"\nexport PATH\n' "$VIRTUAL_ENV" > /etc/profile.d/10-venv.sh
+
 RUN npm install -g @anthropic-ai/claude-code

 COPY requirements.txt /tmp/requirements.txt
 RUN pip install --no-cache-dir -r /tmp/requirements.txt

-RUN useradd -m -u 1000 -s /bin/bash vscode
+# pyftdi: programs the FT2232H EEPROM over libusb, and (with pyserial) reads the
+# FT2232H channel-B UART directly over libusb for bring-up diagnostics.
+RUN pip install --no-cache-dir pyftdi pyserial
+
+RUN useradd -m -u 1000 -s /bin/bash vscode \
+ && echo 'vscode ALL=(ALL) NOPASSWD:ALL' > /etc/sudoers.d/vscode \
+ && chmod 0440 /etc/sudoers.d/vscode

 USER vscode

@@ -8,8 +8,15 @@
    "workspaceFolder": "/workspace",
    "workspaceMount": "source=${localWorkspaceFolder},target=/workspace,type=bind,consistency=cached",
    "mounts": [
-        "source=${localEnv:HOME}${localEnv:USERPROFILE}/.claude,target=/home/vscode/.claude,type=bind,consistency=cached"
+        "source=${localEnv:HOME}${localEnv:USERPROFILE}/.claude,target=/home/vscode/.claude,type=bind,consistency=cached",
+        "source=/dev/bus/usb,target=/dev/bus/usb,type=bind"
    ],
+    // --privileged + the /dev/bus/usb bind mount give libusb (iceprog, pyftdi)
+    // access to the FT2232H once it is usbipd-attached into WSL2.  Attach the
+    // device on the Windows host BEFORE opening/rebuilding the container:
+    //   .devcontainer/attach-icebreaker.ps1   (run as Administrator)
+    // New devices attached after start still appear (the bind mount is live).
+    "runArgs": ["--privileged"],
    "customizations": {
        "vscode": {
            "extensions": [
@@ -0,0 +1,17 @@
+# The devcontainer build uses context ".." (the repo root) but only ever COPYs
+# requirements.txt. Keep the context small so a rebuild doesn't ship the whole
+# repo (~333 MB) to the docker daemon.
+.git/
+.venv/
+build/
+hardware/
+docs/
+diagrams/
+examples/
+*.vcd
+*.pcapng
+*.bin
+*.asc
+*.json.gz
+__pycache__/
+*.pyc
@@ -20,8 +20,13 @@ _autosave-*
 .history/
 hardware/re-bba-rb/gerbers
 hardware/sp1_insert/gerbers
+hardware/re-bba-rb/production
 *-bom.csv
 *-cpl.csv
+*.rpt
+# FT2232H EEPROM backup written by flash_ftdi_eeprom.py at runtime
+hardware/re-bba-rb/eeprom-backup.bin
+hardware/re-bba-rb/re-bba-rb-eeprom.bin

 # Editor / OS cruft
 .DS_Store
@@ -22,7 +22,12 @@ W5500 ethernet back-end".
 **Windows host + WSL2 devcontainer — USB flashing setup:**
 1. Install `usbipd-win` (https://github.com/dorssel/usbipd-win/releases)
 2. Run `.devcontainer/attach-icebreaker.ps1` as Administrator before opening the devcontainer
-3. The devcontainer runs `--privileged` to pass through the USB device
+3. The devcontainer runs `--privileged` AND bind-mounts `/dev/bus/usb` so libusb
+   (`iceprog`, `pyftdi`) can see the FT2232H; the `vscode` user flashes via
+   passwordless `sudo` (the USB nodes are root-owned). If you change
+   `.devcontainer/`, **rebuild the container** for it to take effect.
+4. Flashing the re-bba-rb board (bitstream + FT2232H EEPROM) is documented as the
+   `flash-re-bba-rb` skill — see `.claude/skills/flash-re-bba-rb/SKILL.md`.

 **Local venv (outside devcontainer):**
 ```bash
@@ -59,8 +59,10 @@ from exi_bba.bba_top import BBATop
 #   LEDs which are active-low. No physical button exists on this board (the
 #   iCEbreaker's BTN_N was dev-board-only); panel_btn is tied idle instead.
 # RGB status LED (D11=red/rx, D12=green/tx, D13=yellow/ready) is on the
-#   iCE40UP5K's dedicated SB_RGBA_DRV pins 39/40/41 — fixed by the chip
-#   package on any board, not board-specific, so no resource needed here.
+#   iCE40UP5K's dedicated SB_RGBA_DRV pads 39/40/41.  It IS declared as a
+#   "rgb" resource and requested RAW (dir="-") so SB_RGBA_DRV drives the pads
+#   directly — leaving o_RGB* dangling (the old code) never bonds them and the
+#   LEDs stay dark.  See the "rgb" Resource + elaborate() below, and BRINGUP.md.

 # nextpnr P&R options.  The binding constraint is the isolated 54 MHz capture
 # domain (the SPI Mode-3 bit engine); the 24 MHz sync domain has wide margin.
@@ -75,6 +77,26 @@ from exi_bba.bba_top import BBATop
 # sync domain.  Plain --opt-timing is the better baseline.
 _PNR_TIMING_OPTS = "--opt-timing"

+# UART pin override for bring-up.  The re-bba-rb V1 lab unit had its UART_RXD
+# trace (FPGA pin 19 → FT2232H pin 39) severed by a via-repair drill hole, and
+# the 0.5 mm FT2232H pitch is not hand-reworkable.  Set env UART_J4=1 to relocate
+# the UART onto the accessible J4 debug header — DBG0 = J4 pin 2 = FPGA pin 9
+# (FPGA TX), DBG1 = J4 pin 3 = FPGA pin 10 (FPGA RX), GND = J4 pin 1 — so an
+# external USB-UART dongle can drive the shell, bypassing the FT2232H channel B
+# completely.  Unset (default) keeps the normal FT2232H channel-B pins
+# (tx = 19 = UART_RXD net, rx = 18 = UART_TXD net).
+_UART_TX, _UART_RX = ("9", "10") if os.environ.get("UART_J4") else ("19", "18")
+
+# ETH_D3 relocation for the damaged V1 lab unit: the W5100 data bit-3 trace
+# (FPGA pin 28 → W5100 U11 pin 40, top copper) was nicked by a drill hole, and
+# neither the 0.5 mm pin nor the 0.1 mm trace is hand-reworkable.  Set
+# ETH_D3_PIN=<n> to drive W5100 D3 from a coarse J4 header pad instead, and bodge
+# that pad to the W5100 D3 net:  DBG0=9 (J4 pin2), DBG1=10 (J4 pin3),
+# DBG2=11 (J4 pin4), DBG3=12 (J4 pin5), DBG4=6 (J4 pin6).  NOTE pin 9 collides
+# with UART_J4 TX — fine for the W5100/eth test builds (no UART), not for the
+# full UART_J4 design.  Default = 28 (real board).  See BRINGUP.md.
+_ETH_D3 = os.environ.get("ETH_D3_PIN", "28")
+

 class IceBreakerPlatform(LatticeICE40Platform):
    device      = "iCE40UP5K"
@@ -99,7 +121,7 @@ class IceBreakerPlatform(LatticeICE40Platform):
        # W5100 indirect parallel bus
        Resource("w5100", 0,
                 Subsignal("addr",  Pins("42 38", dir="o")),
-                 Subsignal("data",  Pins("34 32 31 28 27 26 25 23", dir="io")),
+                 Subsignal("data",  Pins(f"34 32 31 {_ETH_D3} 27 26 25 23", dir="io")),
                 Subsignal("cs_n",  Pins("43", dir="o")),
                 Subsignal("rd_n",  Pins("37", dir="o")),
                 Subsignal("wr_n",  Pins("36", dir="o")),
@@ -114,11 +136,23 @@ class IceBreakerPlatform(LatticeICE40Platform):
        Resource("ledr", 0, Pins("48", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
        Resource("ledg", 0, Pins("47", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),

-        # UART debug console → FT2232H Channel B.
-        # On the PC: open the second USB serial port at 115200 8N1.
+        # RGB status LED on the iCE40UP5K's dedicated SB_RGBA_DRV pads
+        # (39=D11 red, 40=D12 green, 41=D13 yellow).  Requested RAW (dir="-") in
+        # elaborate and wired straight from the SB_RGBA_DRV hard block — a normal
+        # buffered (dir="o") output fails nextpnr packing:
+        #   "SB_RGB_DRV/SB_RGBA_DRV port connected to more than just package pin!"
+        # (Bug found at bring-up 2026-08-23: these were previously left dangling,
+        # so the rx/tx/ready RGB indicators never lit. See BRINGUP.md item 5.)
+        Resource("rgb", 0,
+                 Subsignal("r", Pins("39", dir="o")),
+                 Subsignal("g", Pins("40", dir="o")),
+                 Subsignal("b", Pins("41", dir="o"))),
+
+        # UART debug console → FT2232H Channel B (or J4 header if UART_J4=1).
+        # On the PC: open the serial port at 115200 8N1.
        Resource("uart", 0,
-                 Subsignal("tx", Pins("19", dir="o")),
-                 Subsignal("rx", Pins("18", dir="i")),
+                 Subsignal("tx", Pins(_UART_TX, dir="o")),
+                 Subsignal("rx", Pins(_UART_RX, dir="i")),
                 Attrs(IO_STANDARD="SB_LVCMOS")),
    ]

@@ -170,20 +204,37 @@ class BBATopSynth(BBATop):
            if self._status_panel:
                ledr = platform.request("ledr", 0)
                ledg = platform.request("ledg", 0)
+                rgb  = platform.request("rgb", 0, dir="-")  # raw pads (no buffer)
                led  = self.panel_led

+                # Green-LED PWM dimming.  Both green emitters are over-bright on
+                # the re-bba-rb V1 (bring-up 2026-08-23): the discrete LED_G/D6
+                # heartbeat has a wrong 49.9 Ohm series resistor (R37, should be
+                # ~330 Ohm), and the RGB green D12 die is very efficient even at
+                # the SB_RGBA_DRV minimum current code.  The current code is
+                # already the minimum, so time-average both greens down with a
+                # low-duty PWM.  Red (D11/LED_R) and yellow (D13) are fine — left
+                # solid.  Tune _GRN_DUTY (0..15, /16 duty) at bring-up; see
+                # BRINGUP.md items 1 & 5.  PWM freq = 24 MHz/16 = 1.5 MHz (no
+                # visible flicker).
+                _GRN_DUTY = 2                       # ~1/8 duty
+                pwm_cnt = Signal(4)
+                grn_pwm = Signal()
+                m.d.sync += pwm_cnt.eq(pwm_cnt + 1)
+                m.d.comb += grn_pwm.eq(pwm_cnt < _GRN_DUTY)
+
                m.d.comb += [
-                    ledg.o.eq(led[0]),      # heartbeat    (active-high LED)
-                    ledr.o.eq(led[1]),      # EXI activity (active-high LED)
+                    ledg.o.eq(led[0] & grn_pwm),  # heartbeat (green) — PWM-dimmed
+                    ledr.o.eq(led[1]),            # EXI activity (red) — fine
                    # all 3 bits idle/released (active-low idle = 1) — no
                    # physical button exists on this board to read
                    self.panel_btn.eq(C(0b111, 3)),
                ]

-                # iCEbreaker RGB LED has no series resistors — must use
-                # SB_RGBA_DRV (raw pad driver with built-in current source).
-                # RGB0=red→rx_act  RGB1=green→tx_act  RGB2=blue→ready
-                # Verify colour-to-element mapping against schematic at bring-up.
+                # RGB LED has no series resistors — must use SB_RGBA_DRV (raw pad
+                # driver with built-in current source).  o_RGB* MUST connect
+                # directly to the pads (rgb.*.io) — a buffered output fails
+                # packing.  RGB0=red→rx  RGB1=green→tx  RGB2=yellow→ready.
                m.submodules.rgb_drv = Instance("SB_RGBA_DRV",
                    p_CURRENT_MODE="0b1",
                    p_RGB0_CURRENT="0b000001",
@@ -191,12 +242,12 @@ class BBATopSynth(BBATop):
                    p_RGB2_CURRENT="0b000001",
                    i_CURREN=Const(1, 1),
                    i_RGBLEDEN=Const(1, 1),
-                    i_RGB0PWM=led[2],
-                    i_RGB1PWM=led[3],
-                    i_RGB2PWM=led[4],
-                    o_RGB0=Signal(name="rgb_r"),
-                    o_RGB1=Signal(name="rgb_g"),
-                    o_RGB2=Signal(name="rgb_b"),
+                    i_RGB0PWM=led[2],              # rx    → red D11   (solid)
+                    i_RGB1PWM=led[3] & grn_pwm,    # tx    → green D12 (PWM-dimmed)
+                    i_RGB2PWM=led[4],              # ready → yellow D13 (solid)
+                    o_RGB0=rgb.r.io,
+                    o_RGB1=rgb.g.io,
+                    o_RGB2=rgb.b.io,
                )

            # ── UART debug console/shell → FT2232H Channel B ───────────────
@@ -0,0 +1,180 @@
+(footprint "LED_1206_ReverseMount_Everlight_24-21"
+	(version 20260206)
+	(generator "pcbnew")
+	(generator_version "10.0")
+	(layer "F.Cu")
+	(descr "Everlight 24-21 series REVERSE-MOUNT 1206 LED. Part mounts on the component (F.Cu) side; light emits DOWN through a PCB light-window to the opposite (bottom / viewing) side. Land pattern is a standard 1206; the central Edge.Cuts light-window is o1.7 mm (datasheet-confirmed, spec 1.7 mm +/-0.1). Parts: C2892757 red / C2980185 green / C424133 amber. Pad 1 = cathode (silk bar side).")
+	(tags "LED reverse-mount 1206 Everlight 24-21 C2892757 C2980185 C424133")
+	(property "Reference" "REF**"
+		(at 0 -1.9 0)
+		(layer "F.SilkS")
+		(uuid "f1c7b965-1e2f-4f9b-8323-037693b45dc5")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Value" "VAL**"
+		(at 0 1.9 0)
+		(layer "F.Fab")
+		(uuid "f677d899-dab5-4e34-b8a7-9ec643551835")
+		(effects
+			(font
+				(size 0.8 0.8)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "7b814d22-58c5-415c-8cfb-2fe48410ce48")
+		(effects
+			(font
+				(size 1.27 1.27)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "a09d9c63-c978-4752-b3d4-45331e0ce1be")
+		(effects
+			(font
+				(size 1.27 1.27)
+			)
+		)
+	)
+	(attr smd)
+	(duplicate_pad_numbers_are_jumpers no)
+	(fp_line
+		(start -2.4 -1)
+		(end -2.4 1)
+		(stroke
+			(width 0.15)
+			(type solid)
+		)
+		(layer "F.SilkS")
+		(uuid "92697e46-79a2-450b-a27b-d7366d52bb93")
+	)
+	(fp_circle
+		(center 0 0)
+		(end 0.85 0)
+		(stroke
+			(width 0.05)
+			(type default)
+		)
+		(fill no)
+		(layer "Edge.Cuts")
+		(uuid "f0c73ac2-4d87-4c3c-a99f-a702766c2628")
+	)
+	(fp_line
+		(start -2.7 -1.35)
+		(end 2.7 -1.35)
+		(stroke
+			(width 0.05)
+			(type solid)
+		)
+		(layer "F.CrtYd")
+		(uuid "b5ad59dd-6801-47e3-888e-f1e77bbe7d1d")
+	)
+	(fp_line
+		(start -2.7 1.35)
+		(end -2.7 -1.35)
+		(stroke
+			(width 0.05)
+			(type solid)
+		)
+		(layer "F.CrtYd")
+		(uuid "c87c834d-5754-4fa7-a4fd-7598ba43e1f6")
+	)
+	(fp_line
+		(start 2.7 -1.35)
+		(end 2.7 1.35)
+		(stroke
+			(width 0.05)
+			(type solid)
+		)
+		(layer "F.CrtYd")
+		(uuid "abcace6a-b285-4e5a-8dc4-e326cb560770")
+	)
+	(fp_line
+		(start 2.7 1.35)
+		(end -2.7 1.35)
+		(stroke
+			(width 0.05)
+			(type solid)
+		)
+		(layer "F.CrtYd")
+		(uuid "7ee65e7b-4a3e-458f-ab93-7a5def98bd28")
+	)
+	(fp_line
+		(start -1.65 -0.95)
+		(end 1.65 -0.95)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(layer "F.Fab")
+		(uuid "7e01a69e-c830-4293-bc6a-ad6770bd6dd6")
+	)
+	(fp_line
+		(start -1.65 -0.6)
+		(end -1.3 -0.95)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(layer "F.Fab")
+		(uuid "7657bf8e-4a2d-4359-80be-594cffaee932")
+	)
+	(fp_line
+		(start -1.65 0.95)
+		(end -1.65 -0.6)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(layer "F.Fab")
+		(uuid "c4ab4093-6d59-42ee-91d8-9ce9fdd6b23b")
+	)
+	(fp_line
+		(start 1.65 -0.95)
+		(end 1.65 0.95)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(layer "F.Fab")
+		(uuid "c22d87d0-8bda-481a-b3a0-8f844b9c68b1")
+	)
+	(fp_line
+		(start 1.65 0.95)
+		(end -1.65 0.95)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(layer "F.Fab")
+		(uuid "709bccbc-e4c2-4a5f-b8ef-b66acd534efc")
+	)
+	(pad "1" smd roundrect
+		(at -1.4 0)
+		(size 0.8 1.8)
+		(layers "F.Cu" "F.Mask" "F.Paste")
+		(roundrect_rratio 0.25)
+		(uuid "997a776b-eeb2-460d-a61e-3588d42b420e")
+	)
+	(pad "2" smd roundrect
+		(at 1.4 0)
+		(size 0.8 1.8)
+		(layers "F.Cu" "F.Mask" "F.Paste")
+		(roundrect_rratio 0.25)
+		(uuid "0a2975d4-8728-4643-b4e7-72c29613931d")
+	)
+	(embedded_fonts no)
+)
@@ -56,8 +56,8 @@
 	(attr smd)
 	(duplicate_pad_numbers_are_jumpers no)
 	(fp_line
-		(start 0.6 -3.2)
-		(end 0.6 -1.8)
+		(start 0.6 -3.125)
+		(end 0.6 -1.875)
 		(stroke
 			(width 0.05)
 			(type default)
@@ -66,8 +66,8 @@
 		(uuid "3aa70938-586c-4a3e-a93d-02a45af703e9")
 	)
 	(fp_line
-		(start 0.6 -3.2)
-		(end 14.4 -3.2)
+		(start 0.6 -3.125)
+		(end 14.4 -3.125)
 		(stroke
 			(width 0.05)
 			(type default)
@@ -76,8 +76,8 @@
 		(uuid "34b53d18-e03e-4fbc-bf7a-c3cb36e989ef")
 	)
 	(fp_line
-		(start 0.6 -1.8)
-		(end 14.4 -1.8)
+		(start 0.6 -1.875)
+		(end 14.4 -1.875)
 		(stroke
 			(width 0.05)
 			(type default)
@@ -86,8 +86,8 @@
 		(uuid "d865b53d-ba89-433e-9e88-6e1c8c56a37b")
 	)
 	(fp_line
-		(start 14.4 -1.8)
-		(end 14.4 -3.2)
+		(start 14.4 -1.875)
+		(end 14.4 -3.125)
 		(stroke
 			(width 0.05)
 			(type default)
@@ -0,0 +1,184 @@
+# re-bba-rb — bring-up TODO / findings (first physical unit)
+
+Findings from bringing up the first assembled V1 board (repaired: 7 shorted
+vias drilled out, some collateral trace damage). Started 2026-08-23. This is a
+running list — items are **not** being worked yet, just recorded.
+
+## Established good so far (context)
+
+- Bitstream flashes + verifies (`iceprog`, channel A); FPGA configures (heartbeat).
+- FT2232H healthy (channel-A MPSSE + channel-B internal loopback both pass).
+- **W5100 clock confirmed GOOD** (Y2 25 MHz crystal oscillating): the on-board
+  diagnostic (`scratchpad/w5100_check.py`) shows solid green — MR software-reset
+  self-clears, which only happens on the internal clock.
+- W5100 register write/read-back works on 7 of 8 data lines.
+
+## Known damage on THIS unit (self-inflicted, from the via repair — not design bugs)
+
+- **UART_RXD trace broken** (FPGA pin 19 → FT2232H pin 39). Workaround built:
+  `UART_J4=1` synth build relocates the UART to the J4 header (DBG0=pin9=TX,
+  DBG1=pin10=RX, GND=J4 pin1) for an external USB-UART/Pi dongle.
+- **ETH_D3 trace broken** (W5100 data bit 3): net `ETH_D3` = FPGA **U9 pin 28**
+  ↔ W5100 **U11 pin 40**. Confirmed by the diagnostic's red blink-code (4 blinks
+  = D3). One bodge needed; bridge the drilled break (scrape to trace copper / a
+  via — no need to touch the 0.5 mm chip pads). Optional: remap the FPGA D3 bit
+  to a spare J4 pad (DBG2=pin11=J4 pin4) to make one end a coarse header pad.
+
+---
+
+## V2 schematic changes already applied (2026-08-25)
+
+- **U7 EEPROM → 93LC56B** (LCSC C6164, MPN 93LC56BT-I/SN, same SOIC-8). Fixes the
+  soft-brick (256 B is the FT2232H's full EEPROM size). [TODO/REVIEW updated]
+- **All 7 LEDs → Everlight 24-21 reverse-mount 1206** (bottom-viewed, top-populated
+  single-side assembly): red D7/D11 = **C2892757** (24-21SURC), green
+  D6/D8/D9/D12 = **C2980185** (24-21/G6C), amber D13 = **C424133** (24-21UYC).
+  All Vf ≈ 2.0 V (3.3 V-rail + SB_RGBA_DRV safe), moderate mcd. New footprint
+  `hardware/LED_1206_ReverseMount_Everlight_24-21.kicad_mod` (pad1=cathode,
+  **ø1.7 mm Edge.Cuts light-window — datasheet-confirmed** 2026-08-28, spec
+  1.7 mm ±0.1). Refdes text is 1.0 mm (JLC silk floor).
+- **LED series resistors R37/R41/R42: 49.9 Ω → 330 Ω** (reused existing part
+  C25104; R38 already 330). ~3.9 mA vs the blinding ~26 mA — closes item 1's
+  resistor half. Green PWM (`_GRN_DUTY`) in gateware still applies to D6/D12; the
+  new green is only 18–45 mcd so it can likely be relaxed.
+- **Gateware (`synth.py`):** RGB drive bug fixed (raw-pad `o_RGB*`) + green PWM
+  dimming — see items 1 & 5.
+
+Still open below: GC_ON handover redesign (#2), the datasheet-aperture verify,
+EXI/W5100 functional validation (needs a working board), plus the ground-plane
+fill for fab.
+
+## TODO
+
+### 1. LED brightness — LED_G and the two transistor-driven LEDs are blindingly bright
+
+**Observation:** `LED_G` (D6, green) and the two transistor-driven LEDs are far
+too bright; `LED_R` (D7, red) is fine.
+
+**Root cause (from netlist):** the series resistors are wrong.
+- `LED_R` (D7, red): **R38 = 330 Ω** → correct brightness (the reference).
+- `LED_G` (D6, green): **R37 = 49.9 Ω** → ~25 mA, blinding.
+- Transistor-driven: **D8** (green, via Q1 S8050) and **D9** (green, via Q2
+  S8550, collector → **R42 = 49.9 Ω** → D9) → same over-drive. (Confirm D8's
+  own series resistor value too.)
+
+**Fix direction:** raise the 49.9 Ω LED series resistors (**R37**, **R42**, and
+D8's) to ~**330 Ω–1 kΩ** to match D7. (The 49.9 Ω value looks copy-pasted from
+the impedance-matching resistors — wrong part for an LED.) The RGB LED
+(D11/D12/D13 via `SB_RGBA_DRV`, `RGB*_CURRENT=0b000001`) is separate and not
+part of this complaint. BOM/PCB change for V2; a rework could tack larger
+resistors on this unit if the brightness is a bench nuisance.
+
+### 2. GC_ON was not a clean on/off (sat at 2.3 V; both handover LEDs on) — FIXED in schematic 2026-08-28
+
+**Observation:** `GC_ON` measures **2.3 V** (not a clean rail). With **both USB
+and GC connected**, both transistor-driven LEDs (D8, D9) are lit — the intent
+was a power-handover indicator with only ever one active (USB vs GC).
+
+**Analysis (from netlist):** `GC_ON` = TPS2116 status (net: U2.8 = mux ST,
+U12.3, FPGA **U9 pin 21**, pulled up by R5 10 k to 3V3; drives Q1 base via R39
+10 k and Q2 base via R40 10 k). The two indicator transistors are complementary
+(Q1 = S8050 NPN, Q2 = S8550 PNP) expecting GC_ON to swing rail-to-rail:
+- At **GC_ON ≈ 2.3 V**, the NPN (Q1, on when base ≳0.7 V) **and** the PNP (Q2, on
+  when base ≲2.6 V) **both conduct** → both D8 and D9 light. There is no clean
+  one-or-the-other point at this intermediate voltage.
+
+**Root cause (identified 2026-08-28):** the intermediate ~2.3 V is **base-loading
+of the open-drain ST node**. When GC is the source, ST is Hi-Z and *should* sit at
+3V3 (R5 pull-up), but Q1's base (through R39 10 k) drags it down — R5‖R39 divide
+3V3 to ~2.0 V — which is low enough that the PNP Q2's V_EB ≈ 1.3 V and it conducts
+too. So both LEDs light, and the FPGA/EN see a soggy 2 V instead of 3V3.
+TPS2116 ST is only characterised to sink **1 mA** (DS: V_OL @ I_ST = 1 mA,
+t_ST @ R_ST = 10 k), so simply strengthening R5 is not allowed.
+
+**Hardware fix — APPLIED 2026-08-28 (schematic):** raise the base resistors and
+modestly lower the pull-up so GC_ON swings clean while ST stays ≤1 mA:
+- **R5 10 k → 5.1 k** (C25905, reuses R6/R7 part)
+- **R39 / R40 10 k → 33 k** (C25779, reuses R1 part)
+Result: GC active → GC_ON ≈ **2.95 V** → Q1 saturates (D8/GC lit), Q2 V_EB ≈
+0.35 V → OFF (D9/USB dark); USB active → ST low (sinks ~0.73 mA < 1 mA) → D9 lit,
+D8 dark. Clean one-hot. **No new BOM lines, no PCB layout change** (resistor value
+swaps only — run "Update PCB from Schematic" so the F.Fab values match). This also
+**resolves the gateware concern below**: GC_ON now reads a solid ~2.95 V (well
+above the iCE40 V_IH) instead of a marginal 2.3 V. D8/D9 = GC/USB is the confirmed
+assignment (TPS2116 ST "low when VIN1 not used", VIN1 = GC priority — see
+REVIEW.md); the B.SilkS labels are correct.
+- ~~**Gateware:** GC_ON marginal at 2.3 V for the FPGA pin-21 read~~ — addressed
+  by the fix above (now ~2.95 V). The "gate all outputs on GC_ON" work (TODO)
+  can now assume a clean level; still verify on the reworked bench unit.
+
+### 3. Functional W5100 test — send a packet capturable in Wireshark (works around broken D3?)
+
+**Goal:** a test bitstream that makes the W5100 transmit a frame on the wire,
+captured with Wireshark on the laptop (magjack J2 → laptop).
+
+**Feasible:** reuse `W5100ParallelMaster` (MACRAW socket 0, or the UDP socket
+path) with a small periodic trigger + a canned frame. Init runs on NCRA/startup.
+
+**Caveat — the broken ETH_D3:** every byte written to the W5100 has data bit 3
+corrupted, so a frame sent *now* would have wrong MAC/ethertype/payload bytes —
+Wireshark might see a malformed frame (or the W5100 may reject a bad length).
+- A garbled frame appearing at all would still prove **TX path + PHY + magnetics**
+  work on the wire.
+- For a **clean, valid** packet capture, do the **ETH_D3 bodge first** (item in
+  "Known damage"). Recommended order: bodge D3 → re-run `w5100_check` (red should
+  go dark) → then this packet test.
+
+### 4. Bit-bang EXI from a Raspberry Pi to test the FPGA's EXI capture
+
+**Goal:** validate the EXI Mode-3 capture front-end without a GameCube, by having
+a Pi emulate the GC EXI master.
+
+**Approach:** Pi SPI **master, Mode 3 (CPOL=1, CPHA=1)**, 3.3 V (both sides
+3.3 V — no shifting). Drive the EXI **device-ID query** and check the response:
+write `0x0000` (2 bytes) then read 4 bytes → must be **`0x04 0x02 0x02 0x00`**.
+In SPI terms: assert CS, clock out `00 00 xx xx xx xx`, the last 4 MISO bytes are
+the device ID. A match proves ExiCapture → register file → MISO end-to-end.
+
+**Connections (FPGA EXI pins):** CLK=44, MOSI=4, MISO=3, CS=45 (INT=46) — reach
+them at the SP1 edge connector J3 or the damper resistors (R21/R25). Map to Pi:
+Pi SCLK→CLK, Pi MOSI→MOSI(FPGA in), Pi MISO←MISO(FPGA out), Pi CE→CS, GND↔GND.
+
+**Notes:** run the Pi SPI **slow** (e.g., 1 MHz) — the capture domain oversamples
+the EXI clock, so a slow clock is *easier* than the real 27 MHz and fully
+exercises the Mode-3 logic + register file. Good first EXI smoke test before
+trusting it against a real console.
+
+### 5. RGB LEDs (D11 red / D12 green / D13 yellow) — drive bug + brightness
+
+Two findings, from lighting them for the first time at bring-up:
+
+**(a) DRIVE BUG — they don't light in the current gateware (functional, not cosmetic).**
+`SB_RGBA_DRV`'s `o_RGB0/1/2` outputs are left as dangling internal signals in
+`synth.py` (and were in the first test builds). nextpnr never bonds them to the
+dedicated RGB pads (pins 39/40/41 — confirmed absent from the PCF), so the driver
+outputs float and **the LEDs never light**. This means the **rx / tx / ready RGB
+indicators are non-functional in the default build.**
+- **Fix (confirmed on the bench):** request the RGB pins *raw* (no SB_IO buffer)
+  and connect the driver outputs directly to the pads:
+  ```python
+  rgb = platform.request("rgbpad", 0, dir="-")   # Resource: r=39 g=40 b=41
+  Instance("SB_RGBA_DRV", ...,
+           o_RGB0=rgb.r.io, o_RGB1=rgb.g.io, o_RGB2=rgb.b.io)
+  ```
+  Connecting through a normal `dir="o"` request fails packing:
+  `ERROR: SB_RGB_DRV/SB_RGBA_DRV port connected to more than just package pin!`
+- **APPLIED 2026-08-23** in `synth.py`: added a raw `rgb` Resource (39/40/41) and
+  wired `o_RGB0/1/2 = rgb.{r,g,b}.io`; the RGB indicators now light.
+
+**(b) BRIGHTNESS — only GREEN (D12) is too bright; red (D11) and yellow (D13)
+are fine.** Measured with the corrected drive at the driver's *minimum* current
+(`CURRENT_MODE` half, `RGBx_CURRENT=0b000001`). The green die is much more
+efficient per mA, so at the same minimum current it's blinding while red/yellow
+look right. Since the current code is already at minimum, the fix is **PWM
+dimming on green only** — feed a low-duty PWM into `RGB1PWM` (green) instead of a
+static `1`, and leave red/yellow (`RGB0PWM`/`RGB2PWM`) driven solid.
+- **APPLIED 2026-08-23** in `synth.py`: a `_GRN_DUTY` (default 2/16 ≈ 1/8) PWM now
+  gates **both** green emitters — `RGB1PWM` (D12) and `LED_G`/D6 (the discrete
+  heartbeat, over-bright from R37 — item 1). Red/yellow/LED_R stay solid. Tune
+  `_GRN_DUTY` (0..15) at the bench. Gateware mitigation; the proper V2 hardware
+  fix for D6 is still R37 → ~330 Ω (item 1).
+
+### 6. (reserved — Dennis to add)
+
+_Placeholder for the item Dennis was trying to recall._
@@ -34,7 +34,7 @@ lands 2×N off instead of correct.

 ## How to reapply — copy this exact dict, don't reconstruct it from memory

-This is the complete, current correction set (all 16 parts). **Copy-paste
+This is the complete, current correction set (all 20 parts). **Copy-paste
 this block, don't retype it from the table below or from memory** — the one
 time it was retyped from a section of prose instead of copied whole, U4 got
 silently dropped and shipped with a wrong rotation.
@@ -49,12 +49,17 @@ corrections = {
    'D1': -90, 'D4': -90, 'D5': -90, 'U12': -90,     # SOT-23-6, reconstructed hypothesis
    'U1': -180,                                      # SOT-23-5, confirmed (two -90 corrections)
    'U4': -90,                                       # SOT-23-5, confirmed ("U4 is good")
-    'Q1': 180, 'Q2': 180,                            # SOT-23 bottom layer, confirmed "upside down"
+    'Q1': 180, 'Q2': 180,                            # SOT-23; moved bottom->F.Cu in the 2026-08-28 rework, +180 re-confirmed on the top side (JLC preview)
    'D2': -90,                                       # custom footprint, confirmed "90 CW"
    'D3': 180,                                       # SMA diode, confirmed "180"
    'C65': 180,                                      # electrolytic cap, confirmed "180"
    'U2': -90,                                       # SOT-583-8, confirmed "90 CW"
    'U3': 180,                                       # custom SOT95P280X110-6N footprint, confirmed "180"
+    # LED rework 2026-08-28: 7 LEDs -> reverse-mount 1206 (hardware:LED_1206_ReverseMount_Everlight_24-21),
+    # and the "Moved all components to F.Cu" commit put every part (incl. the former bottom-layer D8/D9/Q1/Q2)
+    # on the top side. Only the GREEN 24-21 parts (C2980185) need a flip — their die polarity is opposite the
+    # red (C2892757) / yellow (C424133) parts of the SAME footprint, so D7/D11/D13 take NO correction.
+    'D6': 180, 'D8': 180, 'D9': 180, 'D12': 180,     # GREEN 24-21 only — confirmed via JLC placement preview 2026-08-28
 }   # positive = CCW, negative = CW

 with open('re-bba-rb-cpl.csv', newline='') as f:
@@ -100,8 +105,11 @@ it."
  entirely on that same weakened report. Treat both as **unverified**, not
  settled — re-check them in the placement preview before assembly. Do not
  cite "all large chips are right" as evidence again.
- **D8, D9 (LED_0603, bottom layer)** — verified 2026-07-31 by tracing the
-  circuit rather than by eye, see "D8/D9 polarity" below. No correction.
+- ~~**D8, D9 (LED_0603, bottom layer)** — no correction.~~ **SUPERSEDED
+  2026-08-28.** D8/D9 were swapped to the reverse-mount 1206 footprint and moved
+  to F.Cu; they now take **+180°** and live in the corrections table (green
+  24-21, C2980185). The old "D8/D9 polarity" tracing section below is retained
+  for the schematic-net polarity logic but its *rotation* conclusion is stale.
 - **J2 (HR911105A magjack, rot=90° in the PCB file)** — not a CPL-rotation
  question (J2 doesn't need per-part correction below, it's not in the CPL
  correction set), but its physical orientation was independently verified:
@@ -127,12 +135,18 @@ Each row: designator, package, raw→corrected, confidence.
 | U12 | SOT-23-6 | 180° | **90°**  | Reconstructed hypothesis — not independently re-confirmed |
 | U1  | SOT-23-5 | 180° | **0°** (two corrections: -90° then another -90°, user-confirmed both times) | **Confirmed** by direct user feedback, twice |
 | U4  | SOT-23-5 | 0°   | **270°** (-90°, the same family correction as D1/D4/D5/U12) | **Confirmed** — user checked and said "U4 is good" after this delta, no second correction needed (unlike U1) |
-| Q1  | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** ("upside down" = 180°, direction-agnostic) |
-| Q2  | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** (same as Q1) |
+| Q1  | SOT-23 (now F.Cu; was bottom) | -90° | **90°** | **Confirmed** ("upside down" = 180°, direction-agnostic; +180 re-confirmed on top after the 2026-08-28 F.Cu move, JLC preview) |
+| Q2  | SOT-23 (now F.Cu; was bottom) | -90° | **90°** | **Confirmed** (same as Q1; re-confirmed on top 2026-08-28) |
 | D2  | custom `SON50P110X213X50-7` | 0°   | **270°** | **Confirmed** ("90° clockwise") |
 | D3  | `Diode_SMD:D_SMA` | 180° | **0°**   | **Confirmed** ("180°", direction-agnostic) |
 | C65 | `Capacitor_SMD:CP_Elec_6.3x7.7` | 0°   | **180°** | **Confirmed** ("180°", direction-agnostic) |
 | U2  | SOT-583-8 | 180° | **90°**  | **Confirmed** ("90° clockwise") |
+| D6  | `hardware:LED_1206_ReverseMount_Everlight_24-21` (green C2980185) | -90° | **90°** (+180°) | **Confirmed** (JLC preview 2026-08-28) |
+| D8  | `…24-21` (green C2980185) | 0°   | **180°** (+180°) | **Confirmed** (JLC preview 2026-08-28) |
+| D9  | `…24-21` (green C2980185) | 180° | **0°** (+180°)   | **Confirmed** (JLC preview 2026-08-28) |
+| D12 | `…24-21` (green C2980185) | -90° | **90°** (+180°)  | **Confirmed** (JLC preview 2026-08-28) |
+| D7, D11 | `…24-21` (red C2892757) | -90° | **-90°** (none) | **Confirmed no correction** — same footprint as the green parts but opposite die polarity (JLC preview 2026-08-28) |
+| D13 | `…24-21` (yellow C424133) | -90° | **-90°** (none) | **Confirmed no correction** (JLC preview 2026-08-28) |

 **"Reconstructed hypothesis" parts (U7, U10, D1, D4, D5, U12) explained:**
 the user reported "SOIC and SOT chips are rotated 90°, direction unsure."
@@ -4509,7 +4509,7 @@
 				(justify left)
 			)
 		)
-		(property "Footprint" "LED_SMD:LED_0603_1608Metric"
+		(property "Footprint" "hardware:LED_1206_ReverseMount_Everlight_24-21"
 			(at 25.4 88.9 180)
 			(hide yes)
 			(show_name no)
@@ -4542,7 +4542,7 @@
 				)
 			)
 		)
-		(property "MPN" "KT-0603Y"
+		(property "MPN" "24-21UYC/S530-A3/TR8"
 			(at 25.4 88.9 180)
 			(hide yes)
 			(show_name no)
@@ -4553,7 +4553,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C2287"
+		(property "LCSC" "C424133"
 			(at 25.4 88.9 180)
 			(hide yes)
 			(show_name no)
@@ -4564,7 +4564,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "Hubei KENTO"
+		(property "Manufacturer" "Everlight"
 			(at 25.4 88.9 180)
 			(hide yes)
 			(show_name no)
@@ -5997,7 +5997,7 @@
 				(justify left)
 			)
 		)
-		(property "Footprint" "LED_SMD:LED_0603_1608Metric"
+		(property "Footprint" "hardware:LED_1206_ReverseMount_Everlight_24-21"
 			(at 246.38 88.9 0)
 			(hide yes)
 			(show_name no)
@@ -6030,7 +6030,7 @@
 				)
 			)
 		)
-		(property "MPN" "KT-0603R"
+		(property "MPN" "24-21SURC/S530-A3/TR8"
 			(at 135.89 327.66 0)
 			(hide yes)
 			(show_name no)
@@ -6041,7 +6041,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "Hubei KENTO"
+		(property "Manufacturer" "Everlight"
 			(at 135.89 327.66 0)
 			(hide yes)
 			(show_name no)
@@ -6052,7 +6052,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C2286"
+		(property "LCSC" "C2892757"
 			(at 135.89 327.66 0)
 			(hide yes)
 			(show_name no)
@@ -7133,7 +7133,7 @@
 				(justify left)
 			)
 		)
-		(property "Footprint" "LED_SMD:LED_0603_1608Metric"
+		(property "Footprint" "hardware:LED_1206_ReverseMount_Everlight_24-21"
 			(at 25.4 83.82 180)
 			(hide yes)
 			(show_name no)
@@ -7166,7 +7166,7 @@
 				)
 			)
 		)
-		(property "MPN" "KT-0603R"
+		(property "MPN" "24-21SURC/S530-A3/TR8"
 			(at 25.4 83.82 180)
 			(hide yes)
 			(show_name no)
@@ -7177,7 +7177,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C2286"
+		(property "LCSC" "C2892757"
 			(at 25.4 83.82 180)
 			(hide yes)
 			(show_name no)
@@ -7188,7 +7188,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "Hubei KENTO"
+		(property "Manufacturer" "Everlight"
 			(at 25.4 83.82 180)
 			(hide yes)
 			(show_name no)
@@ -9488,7 +9488,7 @@
 				(justify left)
 			)
 		)
-		(property "Footprint" "LED_SMD:LED_0603_1608Metric"
+		(property "Footprint" "hardware:LED_1206_ReverseMount_Everlight_24-21"
 			(at 237.49 88.9 0)
 			(hide yes)
 			(show_name no)
@@ -9521,7 +9521,7 @@
 				)
 			)
 		)
-		(property "MPN" "KT-0603G"
+		(property "MPN" "24-21/G6C-BM1N2L/2A"
 			(at 127 314.96 0)
 			(hide yes)
 			(show_name no)
@@ -9532,7 +9532,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "Hubei KENTO"
+		(property "Manufacturer" "Everlight"
 			(at 127 314.96 0)
 			(hide yes)
 			(show_name no)
@@ -9543,7 +9543,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C12624"
+		(property "LCSC" "C2980185"
 			(at 127 314.96 0)
 			(hide yes)
 			(show_name no)
@@ -9737,7 +9737,7 @@
 				(justify left)
 			)
 		)
-		(property "Footprint" "LED_SMD:LED_0603_1608Metric"
+		(property "Footprint" "hardware:LED_1206_ReverseMount_Everlight_24-21"
 			(at 25.4 86.36 180)
 			(hide yes)
 			(show_name no)
@@ -9770,7 +9770,7 @@
 				)
 			)
 		)
-		(property "MPN" "KT-0603G"
+		(property "MPN" "24-21/G6C-BM1N2L/2A"
 			(at 25.4 86.36 180)
 			(hide yes)
 			(show_name no)
@@ -9781,7 +9781,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C12624"
+		(property "LCSC" "C2980185"
 			(at 25.4 86.36 180)
 			(hide yes)
 			(show_name no)
@@ -9792,7 +9792,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "Hubei KENTO"
+		(property "Manufacturer" "Everlight"
 			(at 25.4 86.36 180)
 			(hide yes)
 			(show_name no)
@@ -10574,7 +10574,7 @@
 				(justify left)
 			)
 		)
-		(property "Value" "49.9"
+		(property "Value" "330"
 			(at 239.522 79.375 0)
 			(show_name no)
 			(do_not_autoplace no)
@@ -10618,7 +10618,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF4999TCE"
+		(property "MPN" "0402WGF3300TCE"
 			(at 5.08 -24.13 0)
 			(hide yes)
 			(show_name no)
@@ -10640,7 +10640,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25120"
+		(property "LCSC" "C25104"
 			(at 5.08 -24.13 0)
 			(hide yes)
 			(show_name no)
@@ -3938,7 +3938,7 @@
 				(justify left)
 			)
 		)
-		(property "Footprint" "LED_SMD:LED_0603_1608Metric"
+		(property "Footprint" "hardware:LED_1206_ReverseMount_Everlight_24-21"
 			(at 33.02 60.96 0)
 			(hide yes)
 			(show_name no)
@@ -3971,7 +3971,7 @@
 				)
 			)
 		)
-		(property "MPN" "KT-0603G"
+		(property "MPN" "24-21/G6C-BM1N2L/2A"
 			(at 33.02 60.96 0)
 			(hide yes)
 			(show_name no)
@@ -3982,7 +3982,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C12624"
+		(property "LCSC" "C2980185"
 			(at 33.02 60.96 0)
 			(hide yes)
 			(show_name no)
@@ -3993,7 +3993,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "Hubei KENTO"
+		(property "Manufacturer" "Everlight"
 			(at 33.02 60.96 0)
 			(hide yes)
 			(show_name no)
@@ -5211,7 +5211,7 @@
 				(justify left)
 			)
 		)
-		(property "Footprint" "LED_SMD:LED_0603_1608Metric"
+		(property "Footprint" "hardware:LED_1206_ReverseMount_Everlight_24-21"
 			(at 48.26 78.74 0)
 			(hide yes)
 			(show_name no)
@@ -5244,7 +5244,7 @@
 				)
 			)
 		)
-		(property "MPN" "KT-0603G"
+		(property "MPN" "24-21/G6C-BM1N2L/2A"
 			(at 48.26 78.74 0)
 			(hide yes)
 			(show_name no)
@@ -5255,7 +5255,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C12624"
+		(property "LCSC" "C2980185"
 			(at 48.26 78.74 0)
 			(hide yes)
 			(show_name no)
@@ -5266,7 +5266,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "Hubei KENTO"
+		(property "Manufacturer" "Everlight"
 			(at 48.26 78.74 0)
 			(hide yes)
 			(show_name no)
@@ -5314,7 +5314,7 @@
 				(justify left)
 			)
 		)
-		(property "Value" "10k"
+		(property "Value" "33k"
 			(at 62.23 61.15 0)
 			(show_name no)
 			(do_not_autoplace no)
@@ -5358,7 +5358,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF1002TCE"
+		(property "MPN" "0402WGF3302TCE"
 			(at 62.23 57.15 0)
 			(hide yes)
 			(show_name no)
@@ -5369,7 +5369,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25744"
+		(property "LCSC" "C25779"
 			(at 62.23 57.15 0)
 			(hide yes)
 			(show_name no)
@@ -5758,7 +5758,7 @@
 				(justify left)
 			)
 		)
-		(property "Value" "49.9"
+		(property "Value" "330"
 			(at 36.83 56.07 0)
 			(show_name no)
 			(do_not_autoplace no)
@@ -5802,7 +5802,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF4999TCE"
+		(property "MPN" "0402WGF3300TCE"
 			(at 36.83 52.07 0)
 			(hide yes)
 			(show_name no)
@@ -5813,7 +5813,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25120"
+		(property "LCSC" "C25104"
 			(at 36.83 52.07 0)
 			(hide yes)
 			(show_name no)
@@ -7123,7 +7123,7 @@
 				(justify left)
 			)
 		)
-		(property "Value" "49.9"
+		(property "Value" "330"
 			(at 52.07 76.39 0)
 			(show_name no)
 			(do_not_autoplace no)
@@ -7167,7 +7167,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF4999TCE"
+		(property "MPN" "0402WGF3300TCE"
 			(at 52.07 72.39 0)
 			(hide yes)
 			(show_name no)
@@ -7178,7 +7178,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25120"
+		(property "LCSC" "C25104"
 			(at 52.07 72.39 0)
 			(hide yes)
 			(show_name no)
@@ -7314,7 +7314,7 @@
 				(justify left)
 			)
 		)
-		(property "Value" "10k"
+		(property "Value" "5.1k"
 			(at 132.08 44.45 0)
 			(show_name no)
 			(do_not_autoplace no)
@@ -7358,7 +7358,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF1002TCE"
+		(property "MPN" "0402WGF5101TCE"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -7380,7 +7380,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25744"
+		(property "LCSC" "C25905"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -8143,7 +8143,7 @@
 				(justify left)
 			)
 		)
-		(property "Value" "10k"
+		(property "Value" "33k"
 			(at 17.78 72.58 0)
 			(show_name no)
 			(do_not_autoplace no)
@@ -8187,7 +8187,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF1002TCE"
+		(property "MPN" "0402WGF3302TCE"
 			(at 17.78 68.58 0)
 			(hide yes)
 			(show_name no)
@@ -8198,7 +8198,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25744"
+		(property "LCSC" "C25779"
 			(at 17.78 68.58 0)
 			(hide yes)
 			(show_name no)
@@ -42,6 +42,15 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
  FPGA-GC_ON use. USB-only fallback verified via truth table (MODE≤0.35 V row).
  PR1 divider was marginal (1.10 V vs VREF 1.0±8 %) → **fixed: R3=150k**
  (switchover 2.30–2.70 V). Abs max (6 V) fine.
+  **D8/D9 handover-indicator base-loading fixed 2026-08-28:** the complementary
+  Q1(NPN)/Q2(PNP) indicator bases hung on the open-drain ST/GC_ON node through
+  R39/R40 10 k; with R5 10 k they divided GC_ON to ~2 V on GC power, turning BOTH
+  LEDs on and giving the FPGA/EN a soggy level (BRINGUP #2). ST is only
+  characterised to 1 mA sink, so R5 can't just be strengthened. Fix: **R5 10k→5.1k
+  (C25905), R39/R40 10k→33k (C25779)** → GC_ON ≈ 2.95 V on GC (Q1 sat / Q2 off,
+  D8=GC only), ST sinks ~0.73 mA on USB (Q2 on, D9=USB only). Clean one-hot;
+  reuses existing parts; no PCB layout change. D8=GC / D9=USB assignment confirmed
+  (ST low when VIN1 not used, VIN1=GC priority).
 - **AP2112K-1.2 (U1) / AP2112K-3.3 (U4)**: 1 µF X5R in/out present (DS
  requirement), 600 mA rating vs load fine, dropout headroom checked (1.2 V
  version has 1.0–1.3 V dropout — OK from 3.3 V), EN=VIN OK.
@@ -74,8 +83,34 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
  change); TEST→GND, AGND→GND.
 - **EEPROM 93LC46B (U7)**: interface **was wrong** (DO+DI both direct to
  EEDATA) → fixed per DS Table 3.4: EE_DO net, R30 2.2k (C25879) to EE_DATA,
-  R31 10k (C25744) pull-up to 3V3, DI direct. 93LC46B = fixed 16-bit org =
-  correct for FT2232H. Verified in netlist.
+  R31 10k (C25744) pull-up to 3V3, DI direct. 93LC46B = fixed 16-bit org (that
+  part of the earlier verdict stands). **Interface wiring verified in netlist.**
+- **⚠️ U7 PART IS UNDERSIZED — found at bring-up 2026-08-22 (overturns the old
+  "93LC46B = correct for FT2232H" note, which only checked ORG, not size).**
+  The 93LC46B is **1 Kbit = 128 bytes**; the FT2232H addresses a **256-byte**
+  EEPROM (`max_eeprom_size=256`) and its config does not fit in 128 B. FTDI
+  specs a **93LC56B (256 B)** or 93LC66B for the H-series — the 93LC46 is for the
+  FT232R / FT2232**D**. Empirical evidence (pyftdi on the repaired V1 unit): the
+  128-byte chip mirrors into the upper half (`has_mirroring=True`); a config
+  write mirror-clobbers word 0x80→0x00 and **fails verify at word 0x02**; and
+  `set_property` indexes past byte 128. **Consequence:** the "re-BBA-rb" product
+  string CANNOT be stored on V1 — and worse, **attempting the write SOFT-BRICKS
+  the FT2232H** (confirmed 2026-08-22): the partial/mirrored write leaves a
+  checksum-valid-but-garbage config, and the FT2232H then **fails USB enumeration
+  entirely** (dead silent — no `dmesg` attach at all). It does NOT cleanly fall
+  back to ROM defaults; only a BLANK or checksum-INVALID EEPROM does that. (An
+  earlier note here wrongly said a bad EEPROM always falls back and still
+  enumerates — that is FALSE for a partial write; corrected.)
+  **RECOVERY (done on this unit, works):** short U7's **CLK to GND while powering
+  on** so the FT2232H can't read a valid EEPROM → forces ROM defaults →
+  enumerates → then **erase U7** (`flash_ftdi_eeprom.py --erase --commit`, or
+  FT_PROG). Classic FTDI EEPROM recovery. With U7 blank the board runs on ROM
+  defaults ("Dual RS232-HS", 0403:6010); iceprog (bitstream flash — VERIFY OK on
+  this unit) + the channel-B UART are unaffected.
+  **DO NOT run the string write on this board.** `flash_ftdi_eeprom.py` now
+  detects the mirroring and refuses (use --force only to deliberately re-soft-
+  brick for testing; `--erase` blanks). **Fix for a future rev:** fit a 93LC56B
+  at U7 (same SOIC-8, fixed 16-bit org, pin-compatible).
 - **EE_CS pull-down (R43, 10 kΩ) — ADDED 2026-07-31.** FT2232H DS Table 3.4
  states EECS/EECLK/EEDATA are all **"Tri-State during device reset"**, so CS
  floats while the FT2232H is in reset. The Microchip 93LC46B DS is explicit:
@@ -102,7 +137,10 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
  CDONE=ADBUS6, CRESET=ADBUS7 (verified against iceprog.c; old ADBUS3/ACBUS0/
  ACBUS1 now NC). R11/R12 10k pull-ups on CRESET/CDONE intact.
 - **EEPROM contents decision**: ship blank (default 0403:6010 = what iceprog
-  opens). Documented in TODO.
+  opens). Documented in TODO. **Update 2026-08-22:** on V1 this is now *forced*
+  blank, not just a choice — U7 (93LC46B) is too small to hold an FT2232H config
+  (see the U7-undersized note above), so the product string can't be programmed
+  until a 93LC56B is fitted. Blank is the correct, working state.

 ## 4. FPGA sheet (`Fpga.kicad_sch`) — FULLY REVIEWED, PASS

@@ -137,6 +137,29 @@ Major work this session:
        convenience one-command multi-seed workflow needs debugging if
        wanted again.

+## V2 rework — silkscreen & mechanical (added 2026-08-28)
+
+Cosmetic/mechanical items for the in-progress V2 rework (EEPROM→93LC56B,
+reverse-mount LEDs, J3 slot already done). These are PCB-layout tasks, not
+schematic changes.
+
+- [x] **1. Add the project name in silkscreen — DONE 2026-08-28** (commit
+      "Added Silkscreen labels"). "ReBBArb V2" (2 mm) on B.SilkS, mid-board.
+      Free-floating over some copper (silk_over_copper warning, JLC clips it) —
+      reposition to taste if wanted.
+- [ ] ~~**2. Extend the board to the ethernet socket for a flush GC fit.**~~
+      **DROPPED 2026-08-28** — Dennis decided against extending the outline;
+      board ships at its current length.
+- [x] **3. Back-side silkscreen LED legends — DONE 2026-08-28** (same commit).
+      On B.SilkS (mirrored): RX (D11) / TX (D12) / RDY (D13) / HB (D6, heartbeat)
+      / EXI (D7) as vertical labels above the LED-window row; USB (D9) / GC (D8)
+      above the two power LEDs. Semantics confirmed against `synth.py`.
+      D8/D9 = GC/USB assignment **confirmed** (TPS2116 ST low when VIN1 not used,
+      VIN1 = GC priority) and the handover indicator **circuit fixed** 2026-08-28
+      (R5 10k→5.1k, R39/R40 10k→33k — see BRINGUP #2 / REVIEW.md), so the labels
+      are correct and the indicator is now clean one-hot. "ReBBArb V2" name
+      position confirmed fine by Dennis.
+
 ## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18)

 - [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
@@ -358,6 +381,23 @@ Major work this session:

 ## Minor / BOM

+- [x] **U7 EEPROM undersized — swap 93LC46B → 93LC56B — DONE (schematic,
+      2026-08-25):** U7 now 93LC56B, MPN 93LC56BT-I/SN, LCSC **C6164**, same
+      SOIC-8 footprint. 256 B is the FT2232H's full EEPROM size (confirmed:
+      pyftdi `EXT_EEPROM_SIZES=(128,256)`, `max_eeprom_size=256`), so this fully
+      resolves the soft-brick. Found at bring-up 2026-08-22. The 93LC46B is 128 B; the FT2232H needs ≥256 B (93LC56B /
+      93LC66B) to hold its config, so the "re-BBA-rb" USB product string can't be
+      programmed on V1. **⚠️ Worse than cosmetic: ATTEMPTING the write SOFT-BRICKS
+      the FT2232H** — the partial/mirrored write leaves a checksum-valid-garbage
+      config and the chip then fails USB enumeration entirely (dead silent, no
+      dmesg). It does NOT fall back to ROM defaults; only a blank/invalid EEPROM
+      does. **Recovery (done, works):** power on with U7 CLK shorted to GND →
+      forces ROM defaults → enumerates → then erase U7. See REVIEW.md "U7 PART IS
+      UNDERSIZED". **Do NOT run the string write on V1** (`flash_ftdi_eeprom.py`
+      refuses via mirroring detection). Blank U7 is the correct state: iceprog
+      bitstream flash (VERIFY OK on the repaired unit) + the channel-B UART work
+      normally. 93LC56B is the same SOIC-8 / fixed-16-bit-org, pin-compatible
+      drop-in (e.g. 93LC56BT-I/SN) for the respin.
 - [x] RSET_BG 12.4 k — ACCEPTED 2026-07-18 (closed, no change): datasheet
      says 12.3 kΩ, but that is an E192 value with no JLC Basic part —
      WIZnet's own reference synthesizes it as 12 k + 300 Ω. The 0.8 %
@@ -10006,7 +10006,7 @@
 				)
 			)
 		)
-		(property "Value" "93LC46B"
+		(property "Value" "93LC56B"
 			(at 238.506 229.108 0)
 			(show_name no)
 			(do_not_autoplace no)
@@ -10049,7 +10049,7 @@
 				)
 			)
 		)
-		(property "MPN" "93LC46BT-I/SN"
+		(property "MPN" "93LC56BT-I/SN"
 			(at -73.66 5.08 0)
 			(hide yes)
 			(show_name no)
@@ -10071,7 +10071,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C16253"
+		(property "LCSC" "C6164"
 			(at -73.66 5.08 0)
 			(hide yes)
 			(show_name no)
@@ -0,0 +1,67 @@
+#!/usr/bin/env python3
+"""EXI device-ID query for re-bba-rb bring-up — run on a Raspberry Pi wired to
+the FPGA's EXI pins, to validate the GameCube-facing capture path with NO W5100
+involved (so it works even on a unit whose W5100/ethernet side is dead).
+
+It bit-bangs the EXI SPI the way the GameCube does: CLK idles HIGH; the FPGA
+samples MOSI on the falling edge and drives MISO on the rising edge.  It sends
+the device-ID read header (read 4 bytes @ addr 0 = 0x00 0x03), then pauses (the
+GC pauses the clock between the header and the data so the FPGA can prefetch the
+response), then clocks read bytes and looks for the reply 04 02 02 00.
+
+Wiring (Pi BCM GPIO -> FPGA EXI, all 3.3 V, shared GND):
+  CLK  -> EXI CLK  (FPGA pin 44)
+  MOSI -> EXI MOSI (FPGA pin 4, an FPGA *input*)
+  MISO <- EXI MISO (FPGA pin 3, an FPGA *output*)
+  CS   -> EXI CS   (FPGA pin 45)
+  GND  <-> GND
+Reach these at the SP1 edge connector (J3) or on the series damper resistors.
+Edit the BCM pin numbers below to match your wiring.  Run: sudo python3 exi_devid_rpi.py
+
+Requires the FPGA to be running the full BBA design (e.g. build/seed3/top.bin)
+and its 12 MHz clock (X1) alive — both independent of the W5100.
+"""
+import time
+try:
+    import RPi.GPIO as GPIO
+except ImportError:
+    raise SystemExit("needs RPi.GPIO  ->  sudo apt install python3-rpi.gpio")
+
+# ---- set these to your actual Pi BCM pin numbers ----
+CLK, MOSI, MISO, CS = 11, 10, 9, 8
+
+GPIO.setmode(GPIO.BCM)
+GPIO.setup(CLK,  GPIO.OUT, initial=1)   # CPOL=1: clock idles HIGH
+GPIO.setup(MOSI, GPIO.OUT, initial=0)
+GPIO.setup(CS,   GPIO.OUT, initial=1)   # inactive HIGH
+GPIO.setup(MISO, GPIO.IN)
+
+
+def xfer(b):
+    """Clock one byte MSB-first; FPGA samples MOSI on falling, drives MISO on rising."""
+    r = 0
+    for i in range(7, -1, -1):
+        GPIO.output(MOSI, (b >> i) & 1)  # MOSI stable while CLK is high
+        GPIO.output(CLK, 0)              # falling edge -> FPGA samples MOSI
+        GPIO.output(CLK, 1)              # rising edge  -> FPGA drives MISO
+        r = (r << 1) | GPIO.input(MISO)
+    return r
+
+
+GPIO.output(CS, 0)                       # assert CS (active low)
+xfer(0x00)                               # header byte 0: read, addr[12:6]=0
+xfer(0x03)                               # header byte 1: addr[5:0]=0, len-1=3 (4 B)
+time.sleep(0.001)                        # gap so the FPGA can prefetch the reply
+resp = [xfer(0x00) for _ in range(6)]    # clock a few read bytes
+GPIO.output(CS, 1)                       # deassert CS
+GPIO.cleanup()
+
+print("read bytes:", " ".join("%02x" % x for x in resp))
+want = [0x04, 0x02, 0x02, 0x00]
+found = any(resp[i:i + 4] == want for i in range(len(resp) - 3))
+if found:
+    print("EXI device-ID 04 02 02 00  ->  FOUND. EXI capture path works!")
+else:
+    print("device-ID not found. Try: swap to mode-2 edges (move the MISO sample "
+          "to just before the falling edge), check wiring/GND, confirm the FPGA "
+          "is running the BBA design and its 12 MHz clock is alive.")
@@ -0,0 +1,189 @@
+#!/usr/bin/env python3
+"""Program the re-bba-rb FT2232H EEPROM so the unit enumerates as "re-BBA-rb".
+
+Uses pyftdi (libusb) — the in-container tool, since debian's libftdi1-2 ships
+only the runtime lib, not the `ftdi_eeprom` binary.  The intended descriptor
+values mirror hardware/re-bba-rb/ftdi_eeprom.conf.
+
+DRY-RUN BY DEFAULT: prints the diff and writes a raw backup, but does NOT touch
+the EEPROM unless you pass --commit.  Keeps the stock VID/PID 0403:6010.
+
+Usage (inside the devcontainer, FT2232H attached):
+    sudo /opt/venv/bin/python hardware/re-bba-rb/flash_ftdi_eeprom.py           # dry-run + backup
+    sudo /opt/venv/bin/python hardware/re-bba-rb/flash_ftdi_eeprom.py --erase --commit  # blank U7
+
+⚠️⚠️ re-bba-rb V1: DO NOT PROGRAM THE STRINGS — IT SOFT-BRICKS THE FT2232H. ⚠️⚠️
+U7 is a 93LC46B (128-byte / 1 Kbit) EEPROM, TOO SMALL for the FT2232H — the
+H-series needs a 93LC56B (256 B) or 93LC66B (the 93LC46 is for the FT232R /
+FT2232D).  The FT2232H config mirrors in the 128-byte chip, so a string write
+lands a PARTIAL, checksum-valid-but-garbage config.  The FT2232H then reads it at
+power-up and **FAILS USB ENUMERATION ENTIRELY** — dead silent, no dmesg attach.
+It does NOT fall back to ROM defaults (only a BLANK / checksum-INVALID EEPROM
+does that).  This was confirmed on hardware 2026-08-22.  The script therefore
+REFUSES the write when it detects mirroring; --force exists only to reproduce the
+soft-brick deliberately.
+
+RECOVERY if U7 ever gets a bad config written (done on the V1 unit, works):
+  1. Power the board on with U7's CLK pin shorted to GND — the FT2232H then can't
+     read a valid EEPROM and enumerates on ROM defaults ("Dual RS232-HS",
+     0403:6010).
+  2. Release the short and immediately blank U7:
+        sudo /opt/venv/bin/python hardware/re-bba-rb/flash_ftdi_eeprom.py --erase --commit
+  (Classic FTDI EEPROM recovery.)  With U7 blank the board is fully functional;
+  iceprog + the channel-B UART work normally.  Fix for a future rev: 93LC56B at U7.
+
+reset_device() is intentionally NOT called — it re-enumerates the FT2232H and can
+drop a usbip attachment; re-plug / re-attach manually instead.
+"""
+import argparse
+import sys
+from pathlib import Path
+
+VID = 0x0403
+PID = 0x6010
+URL = f"ftdi://0x{VID:04x}:0x{PID:04x}/1"
+
+MANUFACTURER = "hashru"
+PRODUCT = "re-BBA-rb"
+SERIAL = "RBBARB001"
+
+BACKUP = Path(__file__).with_name("eeprom-backup.bin")
+
+
+def main() -> int:
+    ap = argparse.ArgumentParser(description=__doc__)
+    ap.add_argument("--commit", action="store_true",
+                    help="actually write the EEPROM (default: dry-run only)")
+    ap.add_argument("--erase", action="store_true",
+                    help="blank U7 to 0xFF (FT2232H falls back to ROM defaults)")
+    ap.add_argument("--force", action="store_true",
+                    help="attempt the string write even if U7 reports mirroring "
+                         "(undersized 93LC46B) — WILL SOFT-BRICK the FT2232H on "
+                         "V1 (fails USB enumeration; recover via CLK-to-GND + erase)")
+    ap.add_argument("--url", default=URL, help=f"pyftdi device URL (default {URL})")
+    args = ap.parse_args()
+
+    try:
+        from pyftdi.eeprom import FtdiEeprom
+    except ImportError:
+        print("pyftdi not installed. In the devcontainer it is preinstalled; "
+              "otherwise: pip install pyftdi", file=sys.stderr)
+        return 2
+
+    eeprom = FtdiEeprom()
+    try:
+        eeprom.open(args.url)
+    except Exception as exc:  # noqa: BLE001 - surface the real libusb error
+        print(f"Could not open {args.url}: {exc}", file=sys.stderr)
+        print("Is the FT2232H usbipd-attached, and are you running under sudo?",
+              file=sys.stderr)
+        return 1
+
+    # 1) Backup the current EEPROM image before any change.
+    try:
+        BACKUP.write_bytes(bytes(eeprom.data))
+        print(f"Backed up current EEPROM ({len(eeprom.data)} bytes) -> {BACKUP}")
+    except Exception as exc:  # noqa: BLE001
+        print(f"WARNING: could not write backup ({exc}); aborting.", file=sys.stderr)
+        eeprom.close()
+        return 1
+
+    # --- Erase mode: blank U7 back to 0xFF (FT2232H then uses ROM defaults). ---
+    if args.erase:
+        return _erase(eeprom, args.commit)
+
+    # ------------------------------------------------------------------
+    # HARDWARE NOTE — U7 on re-bba-rb V1 is a 93LC46B (1 Kbit = 128 bytes).
+    # The FT2232H addresses a 256-byte EEPROM and its config does NOT fit in
+    # 128 bytes: pyftdi sees the 128-byte chip mirror into the upper half
+    # (has_mirroring=True), the config write mirror-clobbers word 0x80->0x00,
+    # and verify fails.  FTDI specs a 93LC56B (256 B) / 93LC66B for the H-series
+    # (the 93LC46 is for the FT232R / FT2232D).  Writing the strings leaves a
+    # PARTIAL checksum-valid-but-garbage config that SOFT-BRICKS the FT2232H: it
+    # then fails USB enumeration entirely (dead silent — does NOT fall back to
+    # ROM defaults).  Recovery: power on with U7 CLK shorted to GND, then --erase.
+    # So REFUSE the write — do not half-brick the chip.
+    # ------------------------------------------------------------------
+    if eeprom.has_mirroring and not args.force:
+        print("\nREFUSING: U7 reports EEPROM mirroring — it is a 128-byte chip "
+              "(93LC46B), too small for the FT2232H's 256-byte config.\n"
+              "Writing the 're-BBA-rb' strings SOFT-BRICKS the FT2232H on this "
+              "board (partial config -> fails USB enumeration; recover by shorting "
+              "U7 CLK to GND at boot then --erase; see header / REVIEW.md).\n"
+              "Use --erase to blank U7; --force ONLY to reproduce the soft-brick.",
+              file=sys.stderr)
+        eeprom.close()
+        return 3
+
+    # Stage a COMPLETE FT2232H default config, then overlay our strings.
+    print(f"\nEEPROM currently blank: {eeprom.is_empty} — staging FT2232H defaults.")
+    eeprom.initialize()
+
+    cfg = eeprom._config  # decoded config dict (no public accessor in pyftdi 0.57)
+    print("\nCurrent (staged-base) descriptors:")
+    print(f"  vendor_id    = 0x{cfg.get('vendor_id', 0):04x}")
+    print(f"  product_id   = 0x{cfg.get('product_id', 0):04x}")
+
+    # Stage the new strings (VID/PID/channel config untouched).
+    eeprom.set_manufacturer_name(MANUFACTURER)
+    eeprom.set_product_name(PRODUCT)
+    eeprom.set_serial_number(SERIAL)
+
+    print("\nStaged descriptors:")
+    print(f"  manufacturer = {MANUFACTURER!r}")
+    print(f"  product      = {PRODUCT!r}")
+    print(f"  serial       = {SERIAL!r}")
+
+    if not args.commit:
+        print("\nDRY-RUN — nothing written. Re-run with --commit to program.")
+        eeprom.close()
+        return 0
+
+    try:
+        eeprom.commit(dry_run=False)
+    except Exception as exc:  # noqa: BLE001
+        print(f"\nWRITE FAILED ({exc}). U7 may be partially written — run with "
+              "--erase to blank it back to ROM-default fallback.", file=sys.stderr)
+        eeprom.close()
+        return 1
+    eeprom.close()
+    # NOTE: do NOT call reset_device() — it re-enumerates the FT2232H, which
+    # drops the usbipd attachment on WSL2. Re-plug / re-attach manually instead.
+    print("\nEEPROM written. Re-attach USB (usbipd) so the host shows 're-BBA-rb'.")
+    return 0
+
+
+def _erase(eeprom, commit: bool) -> int:
+    """Blank U7 to 0xFF so the FT2232H falls back to ROM defaults.
+
+    On the mirrored 128-byte chip pyftdi's 256-byte verify trips even though the
+    0xFF writes land, so we loop and check the actual content instead of trusting
+    commit()'s verify.
+    """
+    if not commit:
+        print("\n--erase DRY-RUN: would write 0xFF over U7. Add --commit to do it.")
+        eeprom.close()
+        return 0
+    for attempt in range(5):
+        data = bytes(eeprom.data)
+        nonff = sum(1 for b in data if b != 0xFF)
+        print(f"erase attempt {attempt}: non-0xFF bytes = {nonff}")
+        if nonff == 0:
+            print("U7 is fully blank — FT2232H will use ROM defaults.")
+            eeprom.close()
+            return 0
+        eeprom.erase(0xFF)
+        try:
+            eeprom.commit(dry_run=False)
+        except Exception as exc:  # noqa: BLE001 - mirrored-chip verify trips; writes still land
+            print(f"  (commit verify raised, expected on mirrored chip: {exc})")
+        # Re-read fresh next loop without reset_device() (which drops usbip).
+        eeprom.sync()
+    print("Could not fully blank U7 after retries — re-run --erase after re-attach.",
+          file=sys.stderr)
+    eeprom.close()
+    return 1
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())
@@ -0,0 +1,45 @@
+# FT2232H EEPROM config for the re-bba-rb board (libftdi `ftdi_eeprom`).
+#
+# NOTE: the devcontainer does NOT ship the `ftdi_eeprom` binary (debian's
+# libftdi1-2 is the runtime lib only). Inside the container program the EEPROM
+# with the pyftdi script instead — it applies the SAME values as this file:
+#     sudo /opt/venv/bin/python hardware/re-bba-rb/flash_ftdi_eeprom.py --commit
+# This .conf remains the value spec, and works as-is with `ftdi_eeprom` on a host
+# that has the libftdi tools, or as a reference when using FT_PROG on Windows.
+#
+# Purpose: give the on-board FT2232H a product string so the unit shows up as
+# "re-BBA-rb" instead of the generic "Dual RS232-HS".
+#
+# SAFE BY DESIGN — this KEEPS the stock VID/PID (0403:6010) and the default
+# dual-channel config, so `iceprog` (MPSSE on interface A) and the channel-B
+# UART keep working exactly as before.  Only the descriptor strings change.
+#
+# ⚠️ Before writing: back up whatever is there (it should be blank/default):
+#     ftdi_eeprom --device i:0x0403:0x6010 --read-eeprom --to-file eeprom-backup.bin
+#   Then flash the bitstream FIRST and confirm iceprog works; program this
+#   EEPROM only after that's proven (the string is cosmetic).
+#
+# Program with:
+#     ftdi_eeprom --device i:0x0403:0x6010 --flash-eeprom ftdi_eeprom.conf
+#   (re-plug the USB afterwards so the host re-reads the descriptors.)
+
+vendor_id=0x0403          # KEEP 0403 — iceprog/D2XX look for this
+product_id=0x6010         # KEEP 6010 — FT2232H default; iceprog looks for this
+max_power=500             # mA; board draws well under this over USB
+
+manufacturer=hashru       # <- your name/org; free text
+product=re-BBA-rb         # <- this is what makes it show as "re-BBA-rb"
+
+use_serial=true
+serial=RBBARB001          # <- optional; bump per unit if you want unique serials
+
+# Bus-powered while flashing over USB (GC not attached).  If you ever program
+# it while powered from SP1 only, this is still fine — it's a hint to the host.
+self_powered=false
+remote_wakeup=false
+
+# Leave the two channels at their FT2232H defaults (UART/serial).  MPSSE (used
+# by iceprog) is a runtime mode on interface A and works regardless, so there
+# is no need to set cha_type/chb_type here.
+
+filename=re-bba-rb-eeprom.bin   # ftdi_eeprom writes the built image here too
@@ -9,6 +9,18 @@
 	(condition "A.memberOfFootprint('J3') || B.memberOfFootprint('J3')")
 	(constraint edge_clearance (min -0.5mm)))

+# Reverse-mount LED light-windows (D6/D7/D8/D9/D11/D12/D13, Everlight 24-21).
+# Each footprint has an Edge.Cuts light-window cutout under the LED body; the
+# datasheet land places the solder pads ~0.15mm from that cutout - below the
+# JLCPCB 0.3mm copper-to-edge default, but the intended, manufacturer-recommended
+# geometry (the copper sits under the part, not exposed). Relax edge_clearance to
+# 0.1mm for these footprints so the deliberate geometry doesn't spam DRC, while
+# still catching a genuinely-too-tight future edit (<0.1mm). Test BOTH items: the
+# violated pair is (pad) vs (the footprint's own Edge.Cuts window segment).
+(rule "Reverse-mount LED light-window - allow pad-to-cutout clearance"
+	(condition "A.memberOfFootprint('D6') || A.memberOfFootprint('D7') || A.memberOfFootprint('D8') || A.memberOfFootprint('D9') || A.memberOfFootprint('D11') || A.memberOfFootprint('D12') || A.memberOfFootprint('D13') || B.memberOfFootprint('D6') || B.memberOfFootprint('D7') || B.memberOfFootprint('D8') || B.memberOfFootprint('D9') || B.memberOfFootprint('D11') || B.memberOfFootprint('D12') || B.memberOfFootprint('D13')")
+	(constraint edge_clearance (min 0.1mm)))
+
 # Power-integrity: flag any power-rail track narrower than its netclass width.
 # A netclass "track width" is only the DEFAULT for new routing - KiCad does NOT
 # enforce it - so without these rules an under-width power trace passes DRC
@@ -124,22 +136,13 @@
 # it's the one thing the routing was actually for.
 #   USB_DP:  0.25mm width / 0.15mm gap -> ~91ohm  (target 90ohm +/-15%)
 #   ETH_DP:  0.20mm width / 0.14mm gap -> ~100ohm (target 100ohm +/-15%)
-# track_width keeps a +/-0.02mm max band (routing precision). diff_pair_gap
-# has NO max: a max bound sounds right but false-flags normal pad fanout,
-# where P/N necessarily diverge for a few mm right at the pad before
-# converging into the coupled run - DRC can't tell that apart from a
-# genuinely uncoupled long run, and real routing hit gaps of 0.65-1.65mm on
-# fanout stubs vs a ~0.16mm max here. min still catches the case that matters
-# (traces routed too close, i.e. below the fab clearance floor); max on gap
-# only matters over a long uncoupled run, which is a length-matching/loss
-# question, not something this board-wide rule can safely judge per-segment.
-#
-# Covers both halves of the D1/D4/D5 split-net TVS pattern: USB_DP now
-# matches FT_DP/FT_DN (D1's chip-side pins) alongside USB_D+/USB_D-, and
-# ETH_DP matches PHY_TX_P/PHY_TX_N/PHY_RX_P/PHY_RX_N (D4/D5's chip-side pins)
-# alongside ETH_TX_P/N and ETH_RX_P/N - see netclass_patterns in
-# re-bba-rb.kicad_pro. Without that, the chip-side half of each pair falls
-# back to Default and silently skips the impedance target.
+# track_width +/-0.02mm tolerance bands are routing precision, not re-derived
+# targets. diff_pair_gap has a min (catches traces routed too close, below fab
+# clearance) and opt, but intentionally NO max: a gap-max false-flags normal pad
+# fanout, where P/N necessarily diverge over a sub-mm stub right at the pads
+# before converging into the coupled run - KiCad can't tell that apart from a
+# genuinely uncoupled long run (a length-matching/loss question, not one this
+# board-wide per-segment rule can judge). Do NOT re-add a diff_pair_gap max.

 (rule "USB differential pair width/gap (target ~90ohm)"
 	(severity error)
@@ -0,0 +1,753 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "apply_defaults_to_fp_barcodes": false,
+        "apply_defaults_to_fp_dimensions": false,
+        "apply_defaults_to_fp_fields": false,
+        "apply_defaults_to_fp_shapes": false,
+        "apply_defaults_to_fp_text": false,
+        "board_outline_line_width": 0.05,
+        "copper_line_width": 0.2,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.05,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": true,
+          "text_position": 0,
+          "units_format": 0
+        },
+        "fab_line_width": 0.1,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.1,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.8,
+          "height": 1.27,
+          "width": 2.54
+        },
+        "silk_line_width": 0.1,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.1,
+        "silk_text_upright": false,
+        "zones": {
+          "border_display_style": 2,
+          "border_hatch_pitch": 0.5,
+          "corner_radius": 0.0,
+          "corner_smoothing": 0,
+          "fill_mode": 0,
+          "hatch_gap": 1.5,
+          "hatch_orientation": 0.0,
+          "hatch_smoothing_level": 0,
+          "hatch_smoothing_value": 0.1,
+          "hatch_thickness": 1.0,
+          "min_clearance": 0.5,
+          "min_island_area": 10.0,
+          "min_thickness": 0.25,
+          "pad_connection": 1,
+          "remove_islands": 0,
+          "thermal_relief_gap": 0.5,
+          "thermal_relief_spoke_width": 0.5
+        }
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "connection_width": "warning",
+        "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
+        "courtyards_overlap": "error",
+        "creepage": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint": "error",
+        "footprint_filters_mismatch": "ignore",
+        "footprint_symbol_field_mismatch": "warning",
+        "footprint_symbol_mismatch": "warning",
+        "footprint_type_mismatch": "ignore",
+        "hole_clearance": "error",
+        "hole_to_hole": "warning",
+        "holes_co_located": "warning",
+        "invalid_outline": "error",
+        "isolated_copper": "warning",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "lib_footprint_issues": "warning",
+        "lib_footprint_mismatch": "warning",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "mirrored_text_on_front_layer": "warning",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "missing_tuning_profile": "warning",
+        "net_conflict": "warning",
+        "nonmirrored_text_on_back_layer": "warning",
+        "npth_inside_courtyard": "error",
+        "padstack": "warning",
+        "pth_inside_courtyard": "error",
+        "shorting_items": "error",
+        "silk_edge_clearance": "warning",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "solder_mask_bridge": "error",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_on_edge_cuts": "error",
+        "text_thickness": "warning",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_angle": "error",
+        "track_dangling": "warning",
+        "track_not_centered_on_via": "ignore",
+        "track_on_post_machined_layer": "error",
+        "track_segment_length": "error",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "tuning_profile_track_geometries": "ignore",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zones_intersect": "error"
+      },
+      "rules": {
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_connection": 0.0,
+        "min_copper_edge_clearance": 0.5,
+        "min_groove_width": 0.0,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.2,
+        "min_microvia_drill": 0.1,
+        "min_resolved_spokes": 2,
+        "min_silk_clearance": 0.0,
+        "min_text_height": 0.8,
+        "min_text_thickness": 0.08,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.2,
+        "min_via_annular_width": 0.1,
+        "min_via_diameter": 0.5,
+        "solder_mask_to_copper_clearance": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "teardrop_options": [
+        {
+          "td_onpthpad": true,
+          "td_onroundshapesonly": false,
+          "td_onsmdpad": true,
+          "td_ontrackend": false,
+          "td_onvia": true
+        }
+      ],
+      "teardrop_parameters": [
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_round_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_rect_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_track_end",
+          "td_width_to_size_filter_ratio": 0.9
+        }
+      ],
+      "track_widths": [],
+      "tuning_pattern_settings": {
+        "diff_pair_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 1.0
+        },
+        "diff_pair_skew_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 0.6
+        },
+        "single_track_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 0.6
+        }
+      },
+      "via_dimensions": [],
+      "zones_allow_external_fillets": false
+    },
+    "ipc2581": {
+      "bom_rev": "",
+      "dist": "",
+      "distpn": "",
+      "internal_id": "",
+      "mfg": "",
+      "mpn": "",
+      "sch_revision": ""
+    },
+    "layer_pairs": [],
+    "layer_presets": [],
+    "viewports": []
+  },
+  "boards": [],
+  "component_class_settings": {
+    "assignments": [],
+    "meta": {
+      "version": 0
+    },
+    "sheet_component_classes": {
+      "enabled": false
+    }
+  },
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        1,
+        1,
+        2,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        1,
+        1,
+        1,
+        1,
+        1,
+        0,
+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        2,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "endpoint_off_grid": "warning",
+      "extra_units": "error",
+      "field_name_whitespace": "warning",
+      "footprint_filter": "ignore",
+      "footprint_link_issues": "warning",
+      "four_way_junction": "ignore",
+      "ground_pin_not_ground": "warning",
+      "hier_label_mismatch": "error",
+      "isolated_pin_label": "warning",
+      "label_dangling": "error",
+      "label_multiple_wires": "warning",
+      "lib_symbol_issues": "warning",
+      "lib_symbol_mismatch": "warning",
+      "missing_bidi_pin": "warning",
+      "missing_input_pin": "warning",
+      "missing_power_pin": "error",
+      "missing_unit": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "same_local_global_label": "warning",
+      "similar_label_and_power": "warning",
+      "similar_labels": "warning",
+      "similar_power": "warning",
+      "simulation_model_issue": "ignore",
+      "single_global_label": "ignore",
+      "stacked_pin_name": "warning",
+      "unannotated": "error",
+      "unconnected_wire_endpoint": "warning",
+      "undefined_netclass": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "re-bba-rb.kicad_pro",
+    "version": 3
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": 2147483647,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.2,
+        "tuning_profile": "",
+        "via_diameter": 0.6,
+        "via_drill": 0.3,
+        "wire_width": 6
+      }
+    ],
+    "meta": {
+      "version": 5
+    },
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": []
+  },
+  "pcbnew": {
+    "last_paths": {
+      "idf": "",
+      "netlist": "",
+      "plot": "",
+      "specctra_dsn": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "annotation": {
+      "method": 0,
+      "sort_order": 0
+    },
+    "bom_export_filename": "${PROJECTNAME}.csv",
+    "bom_fmt_presets": [],
+    "bom_fmt_settings": {
+      "field_delimiter": ",",
+      "keep_line_breaks": false,
+      "keep_tabs": false,
+      "name": "CSV",
+      "ref_delimiter": ",",
+      "ref_range_delimiter": "",
+      "string_delimiter": "\""
+    },
+    "bom_presets": [],
+    "bom_settings": {
+      "exclude_dnp": false,
+      "fields_ordered": [
+        {
+          "group_by": false,
+          "label": "Reference",
+          "name": "Reference",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "Qty",
+          "name": "${QUANTITY}",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "Value",
+          "name": "Value",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "DNP",
+          "name": "${DNP}",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "Exclude from BOM",
+          "name": "${EXCLUDE_FROM_BOM}",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "Exclude from Board",
+          "name": "${EXCLUDE_FROM_BOARD}",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "Footprint",
+          "name": "Footprint",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "Datasheet",
+          "name": "Datasheet",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "Check_prices",
+          "name": "Check_prices",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "Manufacturer",
+          "name": "Manufacturer",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "MF",
+          "name": "MF",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "MP",
+          "name": "MP",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "Package",
+          "name": "Package",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "Price",
+          "name": "Price",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "Purchase-URL",
+          "name": "Purchase-URL",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "SnapEDA_Link",
+          "name": "SnapEDA_Link",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "Availability",
+          "name": "Availability",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "Description",
+          "name": "Description",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "#",
+          "name": "${ITEM_NUMBER}",
+          "show": false
+        }
+      ],
+      "filter_string": "",
+      "group_symbols": true,
+      "include_excluded_from_bom": true,
+      "name": "",
+      "sort_asc": true,
+      "sort_field": "Reference"
+    },
+    "bus_aliases": {},
+    "connection_grid_size": 50.0,
+    "drawing": {
+      "dashed_lines_dash_length_ratio": 12.0,
+      "dashed_lines_gap_length_ratio": 3.0,
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "hop_over_size_choice": 0,
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.375,
+      "operating_point_overlay_i_precision": 3,
+      "operating_point_overlay_i_range": "~A",
+      "operating_point_overlay_v_precision": 3,
+      "operating_point_overlay_v_range": "~V",
+      "overbar_offset_ratio": 1.23,
+      "pin_symbol_size": 25.0,
+      "text_offset_ratio": 0.15
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "reuse_designators": true,
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0,
+    "top_level_sheets": [
+      {
+        "filename": "re-bba-rb.kicad_sch",
+        "name": "ReBBaRb",
+        "uuid": "dbb182a6-d579-468e-b98b-6f0950da9e3a"
+      }
+    ],
+    "used_designators": "#PWR0ffa1,J1-4,#PWR04cfa1,#PWR019b1,#PWR05fc1,#PWR0d1,#PWR0c80c1,R1-18,#PWR0670d1,L1,#PWR0d9d1,#PWR0e1,#PWR035b1,#PWR0Y1-2,#PWR0C1,C1-60,#FLG0USBVBUS1,#PWR08d1,#FLG0USBGND1,#PWR1-41,#PWR45,Y1-2,#FLG0GC3V1,#PWR0772b1,#PWR03d6c1,FB1-3,#FLG01V2ETH1,#PWR076f1,#PWR07dc1,#PWR091b1,#FLG012VEXI1,X1,U1-13,#PWR04fe1,#FLG0SP13V1,#PWR03bde1,#PWR06d1,#PWR0eff1,#PWR090e1,#PWR064c1-2,#PWR0AD1-4,#PWR0fa1-2,#FLG0VPHY1,D1,#PWR082e1,#PWR0b0ce1,#PWR0fb6f1,#PWR0df1,#PWR0SW1-2,#PWR050d1,#PWR0f3c1,#PWR0f1,#PWR0b4ee1,#PWR0c3b1,#PWR0cb1,#PWR09e1,#PWR0a5b1",
+    "variants": []
+  },
+  "sheets": [
+    [
+      "dbb182a6-d579-468e-b98b-6f0950da9e3a",
+      "ReBBaRb"
+    ],
+    [
+      "69f32f10-d46b-43fd-9030-7f4135d40b78",
+      "Power"
+    ],
+    [
+      "64033f5d-a512-44d7-9483-4c31ef84bd56",
+      "Usb Connector"
+    ],
+    [
+      "73763384-ff95-4826-8da6-2de53070e62f",
+      "fpga"
+    ],
+    [
+      "c2ddb95f-8a63-4bb0-b3f2-a27a372fea3a",
+      "ethernet"
+    ],
+    [
+      "1b071f68-b4ea-469c-942f-de06380c9077",
+      "exi"
+    ]
+  ],
+  "text_variables": {},
+  "tuning_profiles": {
+    "meta": {
+      "version": 0
+    },
+    "tuning_profiles_impedance_geometric": []
+  }
+}
@@ -1,6 +1,6 @@
 {
  "board": {
-    "active_layer": 2,
+    "active_layer": 0,
    "active_layer_preset": "",
    "auto_track_width": true,
    "hidden_netclasses": [],
@@ -159,7 +159,7 @@
        "min_text_height": 0.8,
        "min_text_thickness": 0.08,
        "min_through_hole_diameter": 0.2,
-        "min_track_width": 0.1,
+        "min_track_width": 0.2,
        "min_via_annular_width": 0.05,
        "min_via_diameter": 0.3,
        "solder_mask_to_copper_clearance": 0.0,
@@ -535,7 +535,7 @@
        "microvia_drill": 0.1,
        "name": "ETH_DP",
        "pcb_color": "rgba(0, 0, 0, 0.000)",
-        "priority": 5,
+        "priority": 3,
        "schematic_color": "rgba(0, 0, 0, 0.000)",
        "track_width": 0.2,
        "tuning_profile": "",
@@ -543,43 +543,6 @@
        "via_drill": 0.3,
        "wire_width": 6
      },
-      {
-        "bus_width": 12,
-        "clearance": 0.25,
-        "diff_pair_gap": 0.25,
-        "diff_pair_via_gap": 0.25,
-        "diff_pair_width": 0.2,
-        "line_style": 0,
-        "microvia_diameter": 0.3,
-        "microvia_drill": 0.1,
-        "name": "FB_Sense",
-        "pcb_color": "rgba(0, 0, 0, 0.000)",
-        "priority": 7,
-        "schematic_color": "rgba(0, 0, 0, 0.000)",
-        "track_width": 0.15,
-        "tuning_profile": "",
-        "via_diameter": 0.6,
-        "via_drill": 0.3,
-        "wire_width": 6
-      },
-      {
-        "bus_width": 12,
-        "clearance": 0.15,
-        "diff_pair_gap": 0.25,
-        "diff_pair_width": 0.2,
-        "line_style": 0,
-        "microvia_diameter": 0.3,
-        "microvia_drill": 0.1,
-        "name": "LED",
-        "pcb_color": "rgba(0, 0, 0, 0.000)",
-        "priority": 2,
-        "schematic_color": "rgba(0, 0, 0, 0.000)",
-        "track_width": 0.15,
-        "tuning_profile": "",
-        "via_diameter": 0.6,
-        "via_drill": 0.3,
-        "wire_width": 6
-      },
      {
        "bus_width": 12,
        "clearance": 0.15,
@@ -590,7 +553,7 @@
        "microvia_drill": 0.1,
        "name": "Power",
        "pcb_color": "rgba(0, 0, 0, 0.000)",
-        "priority": 1,
+        "priority": 0,
        "schematic_color": "rgba(0, 0, 0, 0.000)",
        "track_width": 0.3,
        "tuning_profile": "",
@@ -608,7 +571,7 @@
        "microvia_drill": 0.1,
        "name": "PowerLV",
        "pcb_color": "rgba(0, 0, 0, 0.000)",
-        "priority": 3,
+        "priority": 1,
        "schematic_color": "rgba(0, 0, 0, 0.000)",
        "track_width": 0.25,
        "tuning_profile": "",
@@ -616,40 +579,6 @@
        "via_drill": 0.3,
        "wire_width": 6
      },
-      {
-        "clearance": 0.1,
-        "diff_pair_gap": 0.25,
-        "diff_pair_width": 0.2,
-        "microvia_diameter": 0.3,
-        "microvia_drill": 0.1,
-        "name": "Signal",
-        "pcb_color": "rgba(0, 0, 0, 0.000)",
-        "priority": 0,
-        "schematic_color": "rgba(0, 0, 0, 0.000)",
-        "track_width": 0.1,
-        "tuning_profile": "",
-        "via_diameter": 0.6,
-        "via_drill": 0.3
-      },
-      {
-        "bus_width": 12,
-        "clearance": 0.15,
-        "diff_pair_gap": 0.25,
-        "diff_pair_via_gap": 0.25,
-        "diff_pair_width": 0.2,
-        "line_style": 0,
-        "microvia_diameter": 0.3,
-        "microvia_drill": 0.1,
-        "name": "Termination",
-        "pcb_color": "rgba(0, 0, 0, 0.000)",
-        "priority": 6,
-        "schematic_color": "rgba(0, 0, 0, 0.000)",
-        "track_width": 0.3,
-        "tuning_profile": "",
-        "via_diameter": 0.6,
-        "via_drill": 0.3,
-        "wire_width": 6
-      },
      {
        "bus_width": 12,
        "clearance": 0.15,
@@ -660,7 +589,7 @@
        "microvia_drill": 0.1,
        "name": "USB_DP",
        "pcb_color": "rgba(0, 0, 0, 0.000)",
-        "priority": 4,
+        "priority": 2,
        "schematic_color": "rgba(0, 0, 0, 0.000)",
        "track_width": 0.25,
        "tuning_profile": "",
@@ -758,274 +687,6 @@
      {
        "netclass": "USB_DP",
        "pattern": "*FT_DN*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "/fpga/LED_G"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "/fpga/LED_R"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*D6-A*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*D7-A*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*D8-A*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*D8-K*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*D9-A*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*D11-K*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*D12-K*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*D13-K*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*Q2-C*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*ETH_A*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*ETH_D*"
-      },
-      {
-        "netclass": "Power",
-        "pattern": "/exi/EXI_GND"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*ETH_RD*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*ETH_WR*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*RSET_BG*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*ETH_INT*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*ETH_RST*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*ETH_CS*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*LED_LNK*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*LED_ACT*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*FLASH_CS*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*FLASH_MISO*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*WP*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*FLASH_SCK*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*FLASH_MOSI*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*CRESET*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*UART_RXD*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*UART_TXD*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*J2-Pad9*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*J2-Pad12*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*CDONE*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*DBG*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*EXI_CLK*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*EXI_CS*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*EXI_INT*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*EXI_MISO*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*EXI_MOSI*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*EE_CLK*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*EE_CS*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*EE_DATA*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*EE_DO*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*RESET*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*CLK12*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*EXTIN*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*GC_ON*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*CC1*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*CC2*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*PR1*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*U8-REF*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*XTAL_*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*OSCI*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*OSCO*"
-      },
-      {
-        "netclass": "Signal",
-        "pattern": "*XSCO*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*Q1-B*"
-      },
-      {
-        "netclass": "LED",
-        "pattern": "*Q2-B*"
-      },
-      {
-        "netclass": "ETH_DP",
-        "pattern": "*MDI_TX_P*"
-      },
-      {
-        "netclass": "ETH_DP",
-        "pattern": "*MDI_TX_N*"
-      },
-      {
-        "netclass": "ETH_DP",
-        "pattern": "*MDI_RX_P*"
-      },
-      {
-        "netclass": "ETH_DP",
-        "pattern": "*MDI_RX_N*"
-      },
-      {
-        "netclass": "PowerLV",
-        "pattern": "*VPHY*"
-      },
-      {
-        "netclass": "Power",
-        "pattern": "GND"
-      },
-      {
-        "netclass": "Power",
-        "pattern": "*VBST*"
-      },
-      {
-        "netclass": "Termination",
-        "pattern": "*C18-Pad1*"
-      },
-      {
-        "netclass": "Termination",
-        "pattern": "*C19-Pad1*"
-      },
-      {
-        "netclass": "FB_Sense",
-        "pattern": "*VFB*"
      }
    ]
  },
@@ -1035,6 +696,7 @@
      "netlist": "",
      "plot": "gerbers/",
      "specctra_dsn": "",
+      "step": "",
      "vrml": ""
    },
    "page_layout_descr_file": ""
@@ -1295,7 +957,7 @@
        "uuid": "dbb182a6-d579-468e-b98b-6f0950da9e3a"
      }
    ],
-    "used_designators": "",
+    "used_designators": "C17,#PWR090e1-3,#PWR44-50,R20-21",
    "variants": []
  },
  "sheets": [
@@ -4,5 +4,4 @@
  (lib (name "TPS562201DDCR")(type "KiCad")(uri "${KIPRJMOD}/../TPS562201DDCR.kicad_sym")(options "")(descr "TPS562201 buck (custom)"))
  (lib (name "HR911105A")(type "KiCad")(uri "${KIPRJMOD}/../HR911105A.kicad_sym")(options "")(descr "HanRun HR911105A RJ45 magjack (custom)"))
  (lib (name "PUSB3AB6Z_ES")(type "KiCad")(uri "${KIPRJMOD}/../PUSB3AB6Z_ES.kicad_sym")(options "")(descr "Nexperia PUSB3AB6Z 6-ch 3.3V 0.15pF TVS array (ElecSuper 2nd source)"))
-  (lib (name "TPS25961")(type "KiCad")(uri "${KIPRJMOD}/../TPS25961.kicad_sym")(options "")(descr "TI TPS25961 eFuse, 6-pin SON (custom)"))
 )
Author	SHA1	Message	Date
Roflin	c0c123e88b	Fixes the GC/USB power led handover	2026-09-02 21:34:17 +02:00
Roflin	ddb33b6a2c	Added Silkscreen labels	2026-09-02 21:14:06 +02:00
Roflin	a12e4af68b	Adds last Todo item, fixes CPL and rotations.	2026-09-02 21:00:08 +02:00
Roflin	34c54d68b0	Reworks the board further	2026-08-28 17:17:54 +02:00
Roflin	009a643698	Moved all components to F.Cu	2026-08-28 10:29:41 +02:00
Roflin	6ba3447e58	Correct EEPROM soft-brick record: partial write on undersized U7 kills enumeration Hardware bring-up correction (Dennis, 2026-08-22): writing the FT2232H product string to the undersized 93LC46B (U7) does NOT harmlessly fail — the partial, mirrored write lands a checksum-valid-but-garbage config, and the FT2232H then FAILS USB enumeration entirely (dead silent, no dmesg attach). It does NOT fall back to ROM defaults; only a blank/checksum-invalid EEPROM does. The earlier claim that "a bad EEPROM always falls back and still enumerates" was WRONG. Recovery (confirmed working): power on with U7 CLK shorted to GND so the FT2232H can't read a valid config -> forces ROM defaults -> enumerates -> then erase U7. Updated REVIEW.md, TODO.md, the flash-re-bba-rb skill (do-not-program warning + recovery, native-Linux troubleshooting), and flash_ftdi_eeprom.py comments/help to state the soft-brick reality. The script already refuses the write on mirroring detection; --force now documented as "reproduce the soft-brick". Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>	2026-08-22 18:57:52 +00:00
Roflin	1a7f0689ab	Enable in-container USB flashing + flash-re-bba-rb skill; find U7 EEPROM undersized Devcontainer now grants libusb access to the FT2232H so iceprog (bitstream) and pyftdi (FT2232H EEPROM) run inside the container: - devcontainer.json: --privileged + /dev/bus/usb bind mount - Dockerfile: sudo (NOPASSWD for vscode; USB nodes are root-owned), libusb-1.0-0, libftdi1-2, pyftdi Add the flash-re-bba-rb skill documenting the procedure (bitstream via best swept seed, optional EEPROM string, troubleshooting, guardrails) and flash_ftdi_eeprom.py (pyftdi, backup-first, dry-run default) + ftdi_eeprom.conf value spec. Bring-up on the repaired V1 unit: bitstream flash VERIFY OK (iceprog build/seed4/top.bin, capture 58.36 MHz). EEPROM product string CANNOT be programmed on V1 — U7 is a 93LC46B (128 B), too small for the FT2232H, which needs a 93LC56B (256 B); the 128 B chip mirrors and the config write fails verify. This overturns the old REVIEW note "93LC46B = correct for FT2232H" (that only checked ORG, not size). Board still works blank -> ROM defaults; iceprog + UART unaffected. Documented in REVIEW.md + TODO.md (swap U7->93LC56B for V2); flash_ftdi_eeprom.py detects the mirroring and refuses the write. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>	2026-08-22 14:44:43 +00:00