# Schematics

Synthesized (RTL-level) schematics of the BBA design, generated from the actual
Amaranth elaboration via yosys + graphviz. Regenerate with:

```bash
python -m exi_bba.diagram            # all of the below
python -m exi_bba.diagram w5100_master   # just one
```

Open the `.svg` files in a browser or VS Code (they're vector — zoom freely).

| File | What it shows | Size |
|---|---|---|
| `bbatop_blocks.svg` | **Top-level block diagram** — BBATop's submodules (ExiCapture, register file, SPRAM arbiter, RX/TX engines, W5100 master, status panel) as boxes with their interconnections. Start here. | 186 cells |
| `spi_mode3_slave.svg` | EXI Mode-3 SPI bit engine (the capture-domain front-end) — shift registers, bit counter, MISO/MOSI logic. | 109 cells |
| `spram_arbiter.svg` | SPRAM priority arbiter — ETH-write-vs-EXI-read mux + the SB_SPRAM read/write ports. | 80 cells |
| `tx_frame_drain.svg` | TX drain FSM — pulls frames from the FIFOs and streams them to the ethernet master with SOF/EOF. | 124 cells |
| `status_panel.svg` | Bring-up panel — heartbeat counter, activity-LED stretchers, button debounce. | 180 cells |
| `rx_frame_assembler.svg` | RX assembler — writes received frames into the SPRAM ring and advances RWP. | 284 cells |
| `w5100_master.svg` | **Full W5100 parallel master** (bus engine + transaction engine + init/TX/RX FSM). Poster-sized (~1100 cells) — zoom in. | 1129 cells |

These are RTL views: real muxes (`$mux`), adders (`$add`), comparators (`$eq`),
and flip-flops (`$dff`/`$adff`) — *not* the post-place LUT soup. The whole
flattened-and-mapped `BBATop` would be ~2300 LUTs and illegible, which is why the
top level is shown as a block diagram and the leaves as per-module RTL.