Roflin
5d9880f9c5
Reads socket-3 / status registers over the indirect bus and streams them on the UART, without resetting the chip, to inspect what a UDP send left behind. First hardware run was inconclusive (socket regs read 0x00 but SIPR/PHYSR didn't match either "state persisted" or "clean reset") -- the FPGA reflash appears to glitch RST_N, so a self-contained configure+send+readback is the reliable next step. Committed as a starting point for that. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
203 lines
9.0 KiB
Python
203 lines
9.0 KiB
Python
"""Read-only W5100 register dump over UART — post-mortem for a UDP send.
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Flash the normal BBA build, fire a `udp broadcast` from the shell, THEN flash
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this: it does NOT reset the W5100 (RST_N is held high by R36's pull-up across the
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FPGA reconfig, so the chip keeps the state the BBA master left), and just READS a
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handful of socket-3 / status registers over the indirect bus and streams them on
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the UART (115200 8N1). That shows what the master actually did:
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SIP=C0 -> SIPR0 = 192 => NETLCKR unlock worked, source IP took
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SMR=02 -> Sn_MR = UDP
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SSR=22 -> Sn_SR = SOCK_UDP (socket really opened)
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SIR=10 -> Sn_IR bit4 SEND_OK set (send completed)
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TRD/TWR -> if TWR advanced past TRD a frame was queued; equal+nonzero = sent
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PHY -> PHYSR0 (link/speed)
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If SIP!=C0 the network config never took; if SSR!=22 the socket never opened; if
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SIR has no SEND_OK the send never finished; if TWR==TRD==0 nothing was queued.
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Build/flash: python -m exi_bba.w5100_regdump --flash (see W5100SelfTest for the
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platform wiring pattern this reuses).
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"""
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from amaranth import *
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# indirect-mode A[1:0] selects
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_A_MR, _A_AR0, _A_AR1, _A_DR = 0b00, 0b01, 0b10, 0b11
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_MR_IND, _MR_AI = 0x01, 0x02
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# registers to read (16-bit indirect addresses), in report order
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_REGS = [
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("SIP", 0x000F), # SIPR0 (192 if unlock+config worked)
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("SMR", 0x0700), # Sn_MR (socket 3)
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("SSR", 0x0703), # Sn_SR
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("SIR", 0x0702), # Sn_IR
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("TRh", 0x0722), # Sn_TX_RD hi
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("TRl", 0x0723), # Sn_TX_RD lo
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("TWh", 0x0724), # Sn_TX_WR hi
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("TWl", 0x0725), # Sn_TX_WR lo
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("PHY", 0x003C), # PHYSR0
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]
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class W5100RegDump(Elaboratable):
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def __init__(self, *, strobe_cycles=3, blink_cycles=3_000_000):
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self._strobe = strobe_cycles
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self._blink = blink_cycles
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self.bus_addr = Signal(2)
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self.bus_data_o = Signal(8); self.bus_data_oe = Signal()
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self.bus_data_i = Signal(8)
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self.cs_n = Signal(init=1); self.rd_n = Signal(init=1)
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self.wr_n = Signal(init=1); self.rst_n = Signal(init=1) # rst_n stays HIGH
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self.uart_tx = Signal(init=1)
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self.vals = Array([Signal(8, name=f"v{i}") for i in range(len(_REGS))])
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self.done = Signal()
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def elaborate(self, platform):
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m = Module()
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STROBE = self._strobe
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# ── bus engine (same as w5100_selftest) ──────────────────────────────
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bus_go=Signal(); bus_rw=Signal(); bus_a=Signal(2); bus_wd=Signal(8)
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bus_rd=Signal(8); bus_done=Signal(); bus_ctr=Signal(range(STROBE+2)); rw_r=Signal()
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a_o=Signal(2); d_o=Signal(8); d_oe=Signal()
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cs_r=Signal(init=1); rd_r=Signal(init=1); wr_r=Signal(init=1)
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m.d.comb += [self.bus_addr.eq(a_o), self.bus_data_o.eq(d_o), self.bus_data_oe.eq(d_oe),
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self.cs_n.eq(cs_r), self.rd_n.eq(rd_r), self.wr_n.eq(wr_r),
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self.rst_n.eq(1)] # NEVER reset the chip
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m.d.sync += bus_done.eq(0)
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with m.FSM(domain="sync", name="bus_fsm"):
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with m.State("IDLE"):
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m.d.sync += [cs_r.eq(1), rd_r.eq(1), wr_r.eq(1), d_oe.eq(0)]
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with m.If(bus_go):
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m.d.sync += [a_o.eq(bus_a), rw_r.eq(bus_rw), cs_r.eq(0), bus_ctr.eq(0)]
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with m.If(bus_rw):
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m.d.sync += [d_o.eq(bus_wd), d_oe.eq(1), wr_r.eq(0)]
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with m.Else():
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m.d.sync += rd_r.eq(0)
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m.next = "STROBE"
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with m.State("STROBE"):
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m.d.sync += bus_ctr.eq(bus_ctr+1)
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with m.If(bus_ctr == STROBE-1):
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with m.If(~rw_r):
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m.d.sync += bus_rd.eq(self.bus_data_i)
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m.d.sync += [rd_r.eq(1), wr_r.eq(1)]
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m.next = "FINISH"
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with m.State("FINISH"):
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m.d.sync += [cs_r.eq(1), d_oe.eq(0), bus_done.eq(1)]
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m.next = "IDLE"
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m.d.comb += [bus_go.eq(0), bus_rw.eq(0), bus_a.eq(0), bus_wd.eq(0)]
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def bwrite(a, d): m.d.comb += [bus_go.eq(1), bus_rw.eq(1), bus_a.eq(a), bus_wd.eq(d)]
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def bread(a): m.d.comb += [bus_go.eq(1), bus_rw.eq(0), bus_a.eq(a)]
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addrs = Array([Const(a, 16) for _, a in _REGS])
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idx = Signal(range(len(_REGS)+1))
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# ── read each register via indirect mode (chip already in IND from the
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# master, but set MR=IND|AI once to be safe) ─────────────────────────
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with m.FSM(domain="sync", name="dump_fsm"):
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with m.State("SETMR"):
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bwrite(_A_MR, _MR_IND | _MR_AI)
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m.next = "SETMR_W"
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with m.State("SETMR_W"):
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with m.If(bus_done): m.d.sync += idx.eq(0); m.next = "AR0"
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with m.State("AR0"):
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bwrite(_A_AR0, addrs[idx][8:16])
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m.next = "AR0_W"
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with m.State("AR0_W"):
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with m.If(bus_done): m.next = "AR1"
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with m.State("AR1"):
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bwrite(_A_AR1, addrs[idx][0:8])
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m.next = "AR1_W"
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with m.State("AR1_W"):
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with m.If(bus_done): m.next = "RDR"
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with m.State("RDR"):
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bread(_A_DR)
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m.next = "RDR_W"
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with m.State("RDR_W"):
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with m.If(bus_done):
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m.d.sync += self.vals[idx].eq(bus_rd)
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with m.If(idx == len(_REGS)-1):
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m.next = "DONE"
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with m.Else():
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m.d.sync += idx.eq(idx+1); m.next = "AR0"
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with m.State("DONE"):
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m.d.comb += self.done.eq(1)
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# ── UART report: "REG SIP=XX SMR=XX SSR=XX SIR=XX TR=XXXX TW=XXXX PHY=XX" ─
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DIV = round(24_000_000 / 115_200)
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# build "R:" + name=val pairs
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parts = b"R:"
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pos = {}
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for name, _ in _REGS:
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parts += b" " + name.encode()[:3] + b"="
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pos[name] = len(parts) # index of the (first) hex digit
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parts += b"00"
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parts += b"\r\n"
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tmpl = list(parts); MSGLEN = len(tmpl)
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rom = Array([Const(b, 8) for b in tmpl])
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def hexch(nib): return Mux(nib < 10, 0x30+nib, 0x37+nib)
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cur = Signal(8); uidx = Signal(range(MSGLEN+1))
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m.d.comb += cur.eq(rom[uidx])
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with m.Switch(uidx):
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for i, (name, _) in enumerate(_REGS):
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p = pos[name]
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with m.Case(p): m.d.comb += cur.eq(hexch(self.vals[i][4:8]))
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with m.Case(p+1): m.d.comb += cur.eq(hexch(self.vals[i][0:4]))
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shift=Signal(10, init=0x3FF); nbits=Signal(range(11)); baud=Signal(range(DIV))
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gap=Signal(range(DIV*30+1))
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m.d.comb += self.uart_tx.eq(shift[0])
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with m.FSM(domain="sync", name="uart_fsm"):
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with m.State("IDLE"):
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with m.If(self.done): m.d.sync += uidx.eq(0); m.next="LOAD"
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with m.State("LOAD"):
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with m.If(uidx == MSGLEN):
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m.d.sync += gap.eq(DIV*30); m.next="GAP"
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with m.Else():
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m.d.sync += [shift.eq(Cat(C(0,1), cur, C(1,1))), nbits.eq(10), baud.eq(DIV-1)]
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m.next="SHIFT"
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with m.State("SHIFT"):
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with m.If(baud==0):
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m.d.sync += baud.eq(DIV-1)
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with m.If(nbits==1):
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m.d.sync += uidx.eq(uidx+1); m.next="LOAD"
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with m.Else():
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m.d.sync += [nbits.eq(nbits-1), shift.eq(Cat(shift[1:], C(1,1)))]
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with m.Else():
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m.d.sync += baud.eq(baud-1)
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with m.State("GAP"):
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m.d.sync += gap.eq(gap-1)
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with m.If(gap==0): m.d.sync += uidx.eq(0); m.next="LOAD"
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return m
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class W5100RegDumpTop(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.domains += ClockDomain("sync")
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m.submodules.hfosc = Instance("SB_HFOSC", p_CLKHF_DIV="0b01",
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i_CLKHFEN=Const(1,1), i_CLKHFPU=Const(1,1), o_CLKHF=ClockSignal("sync"))
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m.submodules.dut = dut = W5100RegDump()
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w5100 = platform.request("w5100", 0)
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uart = platform.request("uart", 0)
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m.d.comb += [
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w5100.addr.o.eq(dut.bus_addr), w5100.data.o.eq(dut.bus_data_o),
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w5100.data.oe.eq(dut.bus_data_oe), dut.bus_data_i.eq(w5100.data.i),
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w5100.cs_n.o.eq(dut.cs_n), w5100.rd_n.o.eq(dut.rd_n),
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w5100.wr_n.o.eq(dut.wr_n), w5100.rst_n.o.eq(dut.rst_n),
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uart.tx.o.eq(dut.uart_tx),
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]
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return m
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if __name__ == "__main__":
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import sys
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if "--build" in sys.argv or "--flash" in sys.argv:
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from exi_bba.synth import IceBreakerPlatform
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IceBreakerPlatform().build(W5100RegDumpTop(), do_program="--flash" in sys.argv,
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name="w5100_regdump", build_dir="build_w5100test")
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print("[built] build_w5100test/w5100_regdump.bin")
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raise SystemExit(0)
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print("use --build or --flash (this module is a hardware read-only probe)")
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