rebbarb/hardware/re-bba-rb/REVIEW.md

re-bba-rb hardware review — coverage record

Purpose of this file: a complete log of what has been reviewed and how, so a future session/agent does not re-do (or re-litigate) this work. Open action items live in TODO.md; this file records coverage and verdicts, including everything that was checked and found correct.

Maintenance rule (binding): whenever a reviewed circuit is changed, or a new review/verification is performed, update the relevant section here in the same commit. If you change something listed as "verified correct", its entry here must be re-verified or marked stale. TODO.md tracks what to do; REVIEW.md tracks what has been established.

Review window: 2026-07-17 … 2026-07-18. Reviewed by Claude (sessions with Dennis), commits 4704dfb…d0426b3. Verification tooling: kicad-cli 10.0.4 netlist/ERC/DRC/BOM exports, ad-hoc netlist parsers (pins.py/nets.py — parse the kicadxml netlist into per-component pin→net tables; recreate trivially), PDF datasheet extraction, WebSearch/WebFetch for parts and reference designs.

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1. Sources reviewed against

Source	Where	Used for
TPS562201, TPS2116, TPS22810, AP2112K, FT2232H, 93LC46B, USBLC6-2SC6, W5100S, iCE40UP5K, W25Q32JV, MC-711-H72, PUSB3AB6 datasheets	datasheets/ (restored from LFS; TPS22810 + PUSB3AB6 added from web)	pin functions, abs max, app circuits
WIZnet W5100S reference schematic V1.1.0 (signal.com.tr mirror)	fetched, read as image	entire MDI/magnetics section, notes 1–7
SD Gecko wiring table (gc-forever wiki), SD2SP2-Pro schematic (github), SP1ETH (github), ETH2GC (github), webhdx IDE-EXI v2 thread (gc-forever t=4843)	fetched	SP1 DO/DI direction, 12 V rail viability
iceprog source (YosysHQ/icestorm/iceprog/iceprog.c)	fetched	FTDI pin convention
JLCPCB/LCSC part pages	fetched per part	every C-number claimed below

2. Power sheet (Power.kicad_sch) — FULLY REVIEWED, PASS

• TPS562201 (U3, 12V→GC_3V3 buck): EN tied to 12 V checked against abs max — legal (VIN/EN max 19 V). VFB ref 0.768 V; 33k/10k divider → 3.30 V, matches DS Table 7-2 (33.2k/10k). L1 3.3 µH = recommended typ; 2×22 µF out within 20–68 µF window; VBST 100 nF pin-to-SW; input 2×10 µF+100 nF. All per datasheet. Do not re-flag EN-at-12V.
• TPS2116 (U2, GC/USB 3V3 mux): MODE tied to VIN1 = priority mode (checked truth table); ST = open-drain "low when VIN1 not used" → GC_ON high on GC power, R5 10k pull-up to 3V3 — polarity correct for U12-EN + FPGA-GC_ON use. USB-only fallback verified via truth table (MODE≤0.35 V row). PR1 divider was marginal (1.10 V vs VREF 1.0±8 %) → fixed: R3=150k (switchover 2.30–2.70 V). Abs max (6 V) fine.
• AP2112K-1.2 (U1) / AP2112K-3.3 (U4): 1 µF X5R in/out present (DS requirement), 600 mA rating vs load fine, dropout headroom checked (1.2 V version has 1.0–1.3 V dropout — OK from 3.3 V), EN=VIN OK.
• TPS22810 (U12, ETH_3V3 switch): EN never floats (GC_ON has R5 pull-up); QOD floating = valid config; CT floating deliberately accepted — DS Table 2: rise ~98 µs at VIN=3.3 V even with CT=0 → ~0.5 A inrush into ~15 µF; a CT cap changes nothing at 3.3 V. Closed — do not re-open.
• 12 V input: D3 SMAJ12A orientation/standoff correct; C65 100 µF is a 25 V SMD electrolytic (Lelon VZH101M1ETR-0607 — not THT, assembly OK); C3/C4 25 V, C6 50 V — ratings verified in BOM.
• 12 V rail viability: verified against webhdx IDE-EXI v2 / M.2 Loader ("3.3V@2A from 12V rail", gc-forever t=4843) — a shipping SP1 product runs the same architecture at higher load. Only remaining bench check: inrush into C65 at GC power-on (expected non-issue).

3. USB sheet (Usb Connector.kicad_sch) — FULLY REVIEWED, PASS after fixes

• USB-C (J1, MC-711-H72): CC1/CC2 with individual 5.1k pull-downs (correct UFP), A/B pairs tied, VBUS caps 10µ+1µ+100n, shield to GND. PASS.
• USBLC6 (D1): in-line on D+/D−, pass-through orientation correct (the historic D+/D− swap was fixed in an earlier session; verified again), VBUS pin on USB_VBUS. PASS.
• FT2232H (U8): all power pins verified against DS pin table — VPHY/VPLL are +3.3 V pins (fed 3V3 via FB1/FB2 + 100 nF — CORRECT; an earlier review note claiming they should be 1.8 V was wrong; do not "fix"). VREGIN=3V3, VREGOUT→VCORE (1.8 V) with 4.7 µF + 3×100 nF on pins 12/37/64; 4×VCCIO decoupled; REF = 12k 1 % to GND (DS requirement); RESET RC (10k/100 nF); 12 MHz crystal Y1 (CL=12 pF part vs 18 pF caps — verified consistent); TEST→GND, AGND→GND.
• EEPROM 93LC46B (U7): interface was wrong (DO+DI both direct to EEDATA) → fixed per DS Table 3.4: EE_DO net, R30 2.2k (C25879) to EE_DATA, R31 10k (C25744) pull-up to 3V3, DI direct. 93LC46B = fixed 16-bit org = correct for FT2232H. Verified in netlist.
• FTDI↔flash/FPGA config pins: rewired 2026-07-18 to stock iceprog convention: SCK=ADBUS0, MOSI=ADBUS1, MISO=ADBUS2, FLASH_CS=ADBUS4, CDONE=ADBUS6, CRESET=ADBUS7 (verified against iceprog.c; old ADBUS3/ACBUS0/ ACBUS1 now NC). R11/R12 10k pull-ups on CRESET/CDONE intact.
• EEPROM contents decision: ship blank (default 0403:6010 = what iceprog opens). Documented in TODO.

4. FPGA sheet (Fpga.kicad_sch) — FULLY REVIEWED, PASS

• iCE40UP5K (U9, 4 units): VCC=1V2 (pins 5/30); VCCIO_0/2 + SPI_VCCIO1 = 3V3, each decoupled; VPP_2V5 on 3V3 (standard practice, iCEbreaker does the same); VCCPLL via 100 Ω + 100 nF + 10 nF (Lattice filter); CDONE/CRESET 10k pull-ups; EP→GND.
• SPI flash (U10 W25Q32JVSS): on the hard-SPI pins (14–17), WP/HOLD 10k pull-ups, shared correctly with FT2232 ADBUS0-2/4 (FTDI Hi-Z at reset; FPGA held in CRESET during FTDI flashing — iCEbreaker-equivalent arrangement).
• Clocks: X1 12 MHz oscillator → CLK12 on pin 20 (G3 global); EXI_CLK on pin 44 (G6 global). Both verified good pin choices.
• Pin map (authoritative, incl. 2026-07-18 debug additions): EXI_MOSI=4 (in), EXI_MISO=3 (out), EXI_CLK=44, EXI_CS=45, EXI_INT=46, ETH bus=23–43, CLK12=20, GC_ON=21, ETH_RST=2, UART FPGA-RX=18/TX=19 (net names are FTDI-perspective!), LED_G=47, LED_R=48, DBG0–4=9/10/11/12/6.
• Debug provisions added 2026-07-18: D6/D7 LEDs + R37/R38, J4 header, TP1/2/4/5 (TP3 on ethernet sheet). Netlist-verified (LED polarity, TPs on global rails, not sheet-local orphans).

5. Ethernet sheet (ethernet.kicad_sch) — FULLY REVIEWED, PASS after fixes

• W5100S straps/pins, all verified against DS pin table: MOD[3:0]=0100 = "010X" parallel bus ✓; SCLK→GND = documented requirement for bus mode ✓; pin 32=MOSI/A0, pin 33=MISO/A1 (matches WIZnet ref) ✓; CSn/RDn/WRn internal pull-ups (IU), DAT0-7 IOU ✓; INTn is push-pull (type OP) — no pull-up needed, do not add one ✓; RSTn is plain input (type IP) → R36 10k to ETH_3V3 added 2026-07-18.
• 1V2 loop: 1V2O → C61 4.7 µF → FB3 100 Ω ferrite → 1V2A+1V2D with 5×100 nF — matches ref topology. 3V3A/3V3D common (ref's inter-rail ferrites are marked optional; single-net accepted).
• RSET_BG: 12.4k 1 % — DS says 12.3k; ACCEPTED (E192 value, WIZnet ref itself uses 12k+300R; 0.8 % immaterial). Closed.
• Crystal Y2: 25 MHz, CL=12 pF part (C9006) vs 18 pF caps → CL≈12 pF ✓ (DS Table 9 wants 12 pF); mandatory external 1 MΩ feedback (R17) present ✓ (DS: "W5100S has no feedback resistor"). FTDI ref-note: no series RExt (ref uses 0 Ω) — accepted.
• MDI section — now implements the WIZnet ref schematic item-for-item: 49.9 Ω×4 (R26–R29, C25120) + 100 nF×2 (C18/C19) termination on the PHY-side nets; 3.3 Ω×4 series dampers (R32–R35, C137986) — chain per line: U11 pin → termination tap → 3.3 Ω → ESD → transformer; C20 100 nF + C21 1 µF center-tap bypass at J2 pins 4/5. Net naming: PHY_* (chip side) / MDI_* (damper→ESD) / ETH_* (ESD→jack); all three groups are in the ETH_DP netclass (patterns in re-bba-rb.kicad_pro).
• D4/D5 (USBLC6 on the pairs) — SETTLED, do not re-litigate: keep. ST rates USBLC6 for Ethernet; 2.5–3.5 pF OK at 100BASE-TX. Two deliberate details: (1) pin 5 floats on purpose (lines are 3.3 V-biased and swing above it; a tied rail would clip peaks; floating rail self-biases and the 6 V zener still clamps); (2) split nets force flow-through routing (pins 1↔6/3↔4 are one internal node) — never merge the nets or stub the diode. Full reasoning in TODO.md.
• Magjack J2 (HR911105A): transformer spec verified vs DS Table 11 (1:1, 350 µH) ✓; LED wiring (R14/R15 330 Ω anodes to ETH_3V3, cathodes to LNKn/ACTn pins 17/20) — assumed internal LED pinout 9/12=anodes, 10/11=cathodes: confirm at bring-up (no HR911105A datasheet in repo). Pin 8 (Bob-Smith common) + shield tied directly to GND — deviation from ref's 1 nF/2 kV chassis split, accepted deliberately (GC floats, no earth).
• Ethernet layout (PCB) — reviewed twice (after rework + after insertion): termination 1–3 mm from U11 MDI pins; dampers in-line, MDI stubs 1.45–1.48 mm; D4/D5 flow-through confirmed pad-by-pad; pair skew TX 0.66 mm / RX 1.81 mm (fine at 100M — do not "improve"); pairs on F.Cu over solid In1 GND, one B.Cu crossover via per N line at the jack; In1 plane correctly voided under the magjack cable/isolation side (deliberate, keep); C20/C21 against the jack pin column (as close as the plane void allows); 30 GND stitch vias in the corner; RX pair passes ~3–4 mm from Y2 (accepted, don't move closer); RSET_BG 2.8 mm with one via to B.Cu (plane-shielded, OK).

6. EXI sheet (exi.kicad_sch) — FULLY REVIEWED, PASS after DO/DI fix

• DO/DI direction — SETTLED with hardware evidence, do not re-litigate: YAGCD SP1 naming is console-perspective: pin 6 DO = GC data out = adapter MOSI input; pin 9 DI = GC data in = adapter MISO output. Evidence: SD Gecko straight-through table (MC pin 5 "DO" → SD CMD input, pin 7 "DI" → SD DAT0 output) + SD2SP2 (DO → OR gate → CMD). The board was wired backwards (following a wrong table in docs/gc_bba_fpga_design.md, since corrected); fixed as a pure rename + R21/R25 identity swap, zero copper changes. Final: J3.6(DO)→R21 22 Ω→FPGA pin 4 = EXI_MOSI; J3.9(DI)→R25 33 Ω→FPGA pin 3 = EXI_MISO.
• PUSB3AB6 (D2): pinout verified vs Nexperia DS (1=CH1, 2=GND any-pin, 3–7=CH2–6); DFN2111-7 matches the SON50P110X213X50-7 footprint; 0.15 pF/ch; rated for 3.3 V lines. Note: BOM part C49383400 is the ElecSuper clone ("(ES)"), pin-compatible — bring-up suspect only if ESD behaviour odd.
• EXTIN: 10k (R18) to SP1_3V3 (the GC's own rail) — correct, doesn't back-power. 12 V: J3.5 → 12V_EXI (power tree). J3.8 (second 3.3 V pin) deliberately NC. Series elements: R24 100 Ω on EXI_CLK (input damping), R21/R25 as above. INT (J3.3) driven by FPGA pin 46 — gateware should use open-drain emulation (TODO).
• J3 footprint provenance: 12 contacts, 1 mm effective pitch, two staggered depth rows, front side only, fingers to the board edge (the .kicad_dru has a J3 edge-clearance exception for this). Geometry comes from the physical sp1_test_plug iterations — the test-plug project has no reusable footprint to diff (it only carries FFC breakouts). Outline/ protrusion fit remain bench checks.

7. PCB global / JLCPCB — REVIEWED, PASS

• DRC: 0 errors / 0 unconnected / 0 parity as of each review point (remaining parity items = the 11 debug/fix footprints awaiting placement + 3 FTDI reroutes + R3 value sync — all listed by F8). Warnings are silkscreen cosmetics only (~150; JLC auto-clips).
• JLC capability floor: encoded as error-severity rules in re-bba-rb.kicad_dru (0.09 mm trace/space, 0.15 mm drill, 0.2 mm hole-to-copper etc.) — passing. Diff-pair impedance rules (USB 90 Ω, ETH 100 Ω) are error-severity and passing; they police PHY_/MDI_/ETH_* and FT_D*/USB_D* via netclass patterns.
• Stackup: 7628 prepreg 0.2104 mm / 0.6 mm core ≈ 1.14 mm total = JLC04121H-7628 (JLC nominal 1.2 mm, satisfies SP1 slot). Order with ENIG + gold fingers + 45° bevel (copper_finish field says "None" — cosmetic only). Board 102×33.4 mm.
• Fiducials: FID1–3 placed 2026-07-18 (board-only footprints) at (195, 68.5)/(131, 48)/(163, 44.5) — track-clearance verified after a first placement attempt collided with tracks (caught by DRC).
• Zones: In1.Cu = single solid GND plane; In2.Cu = 3V3 + ETH_3V3 (priority 1) islands. No other zones.

8. BOM — FULLY AUDITED (netlist-vs-BOM count check passes)

All orderable components carry Footprint+Value+MPN+LCSC+Manufacturer. Deliberate in_bom no: J3 (gold fingers), J4, TP1–5 — the only allowed netlist/BOM delta. Spot-verified on JLC/LCSC: crystals CL=12 pF (C70565/ C9006, Basic), 49.9 Ω C25120, 3.3 Ω C137986 (YAGEO, Extended), 2.2k C25879, 150k C25755, LEDs C72043/C2286 (Basic), 12 V-rail ratings, 1 % tolerances on R1–R4/R10/R16/R26–R38. D2 = ElecSuper clone (see §6).

9. Explicitly NOT reviewed / remaining risk (don't claim coverage)

• Mechanical fit (outline vs slot, RJ45/USB-C protrusion) — bench only.
• HR911105A internal LED pinout — assumed, confirm at bring-up.
• W5100S register map in the gateware — written from memory per CLAUDE.md; confirm at bring-up.
• Actual power-on behaviour (12 V inrush, mux transitions under load, FT2232+iCE40 enumeration) — bench only.
• Gateware (board PCF, GC_ON gating, UART crossover, INT drive style, LED/DBG driving) — tracked in TODO, not part of the hardware review.
• re-bba-rb.kicad_pcb.old.* / .history/ — deleted/ignored, never reviewed for content.

10. Session/history notes an agent may need

• datasheets/ was once deleted by an errant commit and restored from the local LFS object store; recovery recipe is in the git log of 4704dfb.
• A stale case-colliding power.kicad_sch was removed (Windows checkout hazard — never add files differing only in case).
• The SP1 pin table in docs/gc_bba_fpga_design.md was the root cause of the DO/DI swap and has been corrected — trust it now; it carries a "do not swap" note with the evidence.