Roflin
a86aa255f1
Documents everything examined in the 2026-07-17/18 review - not just findings but full coverage with verdicts, so future sessions know what not to re-review: per-sheet verification against datasheets and the WIZnet reference design, the settled look-wrong-but-correct list (VPHY/VPLL on 3.3V, D4/D5 floating VBUS + flow-through, EN at 12V, RSET 12.4k, no CT cap, DO/DI direction evidence), PCB/JLC/BOM audit state, explicit not-reviewed list (bench/gateware items), and a binding rule to keep the file updated in the same commit as any change to a reviewed circuit. Referenced from CLAUDE.md alongside TODO.md. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
145 lines
2.6 KiB
Plaintext
145 lines
2.6 KiB
Plaintext
{
|
|
"board": {
|
|
"active_layer": 2,
|
|
"active_layer_preset": "",
|
|
"auto_track_width": true,
|
|
"hidden_netclasses": [],
|
|
"hidden_nets": [],
|
|
"high_contrast_mode": 0,
|
|
"net_color_mode": 1,
|
|
"opacity": {
|
|
"images": 0.6,
|
|
"pads": 1.0,
|
|
"shapes": 1.0,
|
|
"tracks": 1.0,
|
|
"vias": 1.0,
|
|
"zones": 0.6
|
|
},
|
|
"prototype_zone_fills": false,
|
|
"selection_filter": {
|
|
"dimensions": true,
|
|
"footprints": true,
|
|
"graphics": true,
|
|
"keepouts": true,
|
|
"lockedItems": false,
|
|
"otherItems": true,
|
|
"pads": true,
|
|
"text": true,
|
|
"tracks": true,
|
|
"vias": true,
|
|
"zones": true
|
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},
|
|
"visible_items": [
|
|
"vias",
|
|
"footprint_text",
|
|
"footprint_anchors",
|
|
"ratsnest",
|
|
"grid",
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|
"footprints_front",
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|
"footprints_back",
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|
"footprint_values",
|
|
"footprint_references",
|
|
"tracks",
|
|
"drc_errors",
|
|
"drawing_sheet",
|
|
"bitmaps",
|
|
"pads",
|
|
"zones",
|
|
"drc_warnings",
|
|
"drc_exclusions",
|
|
"locked_item_shadows",
|
|
"conflict_shadows",
|
|
"shapes",
|
|
"board_outline_area",
|
|
"ly_points"
|
|
],
|
|
"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
|
|
"zone_display_mode": 0
|
|
},
|
|
"git": {
|
|
"integration_disabled": false,
|
|
"repo_type": "",
|
|
"repo_username": "",
|
|
"ssh_key": ""
|
|
},
|
|
"meta": {
|
|
"filename": "re-bba-rb.kicad_prl",
|
|
"version": 5
|
|
},
|
|
"net_inspector_panel": {
|
|
"col_hidden": [
|
|
false,
|
|
false,
|
|
false,
|
|
false,
|
|
false,
|
|
false,
|
|
false,
|
|
false,
|
|
false,
|
|
false,
|
|
false,
|
|
false
|
|
],
|
|
"col_order": [
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11
|
|
],
|
|
"col_widths": [
|
|
162,
|
|
147,
|
|
91,
|
|
67,
|
|
91,
|
|
91,
|
|
91,
|
|
71,
|
|
91,
|
|
91,
|
|
91,
|
|
91
|
|
],
|
|
"custom_group_rules": [],
|
|
"expanded_rows": [],
|
|
"filter_by_net_name": true,
|
|
"filter_by_netclass": true,
|
|
"filter_text": "",
|
|
"group_by_constraint": false,
|
|
"group_by_netclass": false,
|
|
"show_time_domain_details": false,
|
|
"show_unconnected_nets": false,
|
|
"show_zero_pad_nets": false,
|
|
"sort_ascending": true,
|
|
"sorting_column": 0
|
|
},
|
|
"open_jobsets": [],
|
|
"project": {
|
|
"files": []
|
|
},
|
|
"schematic": {
|
|
"hierarchy_collapsed": [],
|
|
"selection_filter": {
|
|
"graphics": true,
|
|
"images": true,
|
|
"labels": true,
|
|
"lockedItems": false,
|
|
"otherItems": true,
|
|
"pins": true,
|
|
"ruleAreas": true,
|
|
"symbols": true,
|
|
"text": true,
|
|
"wires": true
|
|
}
|
|
}
|
|
}
|