Roflin
02239466fb
bba_top wired ClockSignal("sync") to ClockSignal("exi"), so the two "domains"
were always the same physical clock net. Everything between them -- six
AsyncFIFOs and three PulseSynchronizers -- was pure latency and logic for a
crossing that did not exist.
* the six AsyncFIFOs become plain SyncFIFOs
* the three PulseSynchronizers become wires
* BBARegisterFile and ExiCapture move from m.d.exi to m.d.sync
* the exi ClockDomain is gone; HFOSC drives sync directly
The SPRAM request write port is also combinational now. A registered w_en
costs a 24 MHz cycle, and the protocol's turnaround byte (~296 ns at 27 MHz)
has no cycles to spare.
Passing: bba_register_file, spram_arbiter, rx_frame_assembler, tx_frame_drain,
w5100_parallel_master, uart_shell, status_panel. bba_top at EXI_HALF=1
(27 MHz, the hardware rate) passes device ID, PAR read/write, NWAYS, RWP and
the 34-byte TX frame.
STILL OPEN: the SPRAM/DMA read is one byte late. Removing the CDC was not
enough -- the remaining round trip is the rx crossing (exiclk->sync, a REAL
CDC, ~125 ns) plus FSM decode plus the spram_req FIFO, arbiter, SPRAM access
and spram_rsp FIFO, which still exceeds the turnaround byte. Next step: now
that it is all one domain, drop the two SPRAM FIFOs entirely and give the
register file a direct request/grant port on the arbiter -- that should take
the round trip to ~2-3 cycles and fit.
exi_capture and exi_j4 testbenches still assert removed behaviour (the CS-fall
flush and the old MISO slot timing) and need rewriting for the clocked engine.
Still WIP -- do not flash.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
278 lines
12 KiB
Python
278 lines
12 KiB
Python
"""ExiCapture — fast EXI byte-capture front-end (capture domain, 54 MHz).
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Wraps the SPIMode3Slave bit engine and bridges it to the slower `exi` domain
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(24 MHz) through two AsyncFIFOs:
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capture (54 MHz) exi (24 MHz)
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┌────────────────────┐ rx_fifo ───► received bytes (header + data)
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│ SPIMode3Slave │ (8-bit, capture→exi)
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│ (bit engine) │ tx_fifo ◄─── response bytes to drive on MISO
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└────────────────────┘ (8-bit, exi→capture)
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Why split: the bit engine must oversample a 27 MHz EXI clock 2×, which needs a
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54 MHz clock — far faster than the register-file logic can close (~44 MHz).
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Only this small, shallow front-end runs fast; everything else stays at 24 MHz.
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TX response gating
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------------------
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Every EXI transaction begins with 2 header bytes (write_flag/addr/len) during
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which the GC ignores MISO. The core cannot have produced a response yet (it
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hasn't even decoded the header), so the wrapper must NOT pop tx_fifo for those
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2 bytes. A per-transaction counter (`txld_cnt`, reset by frame_start) gates the
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pop: header bytes drive a don't-care 0xFF; from the first data byte onward the
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wrapper pops tx_fifo (one byte per tx_load). `tx_hold` is registered at tx_load
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time — before the FIFO advances — so the bit engine latches the correct byte on
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the following SPI rising edge (the classic FWFT-advance off-by-one is avoided).
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"""
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from amaranth import *
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from amaranth.lib.cdc import FFSynchronizer
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from amaranth.lib.fifo import AsyncFIFO
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from exi_bba.spi_mode3_slave import SPIMode3Slave
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__all__ = ["ExiCapture"]
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class ExiCapture(Elaboratable):
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"""EXI front-end: SPI bit engine (capture domain) + byte FIFOs to core.
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Physical SPI pins (capture domain)
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----------------------------------
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spi_clk / spi_mosi / spi_cs_n : raw async inputs from the GC
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spi_miso : output to the GC
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Core-facing RX byte stream (core domain, FWFT read side of rx_fifo)
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------------------------------------------------------------------
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rx_data : current received byte
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rx_rdy : a received byte is available
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rx_en : pop (assert for one core cycle to consume rx_data)
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Core-facing TX byte stream (core domain, write side of tx_fifo)
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--------------------------------------------------------------
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tx_data : response byte to enqueue
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tx_en : write strobe
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tx_rdy : tx_fifo has room
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"""
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def __init__(self, rx_depth=4, tx_depth=2):
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self._rx_depth = rx_depth
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self._tx_depth = tx_depth
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# Physical SPI (capture domain, wired to pins by BBATop)
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self.spi_clk = Signal(init=1)
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self.spi_mosi = Signal()
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self.spi_cs_n = Signal(init=1)
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self.spi_miso = Signal()
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# Core-facing RX read side
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self.rx_data = Signal(8)
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self.rx_rdy = Signal()
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self.rx_en = Signal()
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# Core-facing TX write side
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self.tx_data = Signal(8)
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self.tx_en = Signal()
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self.tx_rdy = Signal()
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# Core-facing: high (exi domain) while a transaction is in progress.
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# The register file uses it to stream variable-length (DMA) reads until
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# CS deasserts.
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self.cs_active = Signal()
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def elaborate(self, platform):
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m = Module()
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# ── Clock domains driven by the EXI clock pin ─────────────────────
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# The bit engine is clocked by EXI CLK itself (pin 44 = die (6,0) =
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# global buffer net 6 on the 5k-sg48, so it can drive a real clock
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# network). Two edges are needed: Mode 3 samples MOSI on the RISING
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# edge and MISO must change on the FALLING edge, between the master's
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# sampling points.
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#
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# Each edge gets TWO domains with the same clock:
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# *_rst async-reset by CS -- the bit/byte counters, which must
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# restart at every transaction
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# (plain) no reset -- the byte FIFOs. Resetting only ONE side of an
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# AsyncFIFO desynchronises its gray pointers and corrupts it,
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# so the FIFOs must NOT see CS.
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m.domains.exiclk = cd_p = ClockDomain(local=True, async_reset=True)
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m.domains.exiclk_n = cd_n = ClockDomain(local=True, async_reset=True,
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clk_edge="neg")
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m.domains.exififo_w = cd_fw = ClockDomain(local=True, reset_less=True)
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# NOTE: both FIFO domains are POSEDGE. AsyncFIFO instantiates a
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# posedge-only reset CDC internally, so a negedge domain cannot host a
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# FIFO side. The engine pops in `exififo_r` (posedge) and hands the
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# byte to its negedge output stage through a register.
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m.domains.exififo_r = cd_fr = ClockDomain(local=True, reset_less=True)
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m.d.comb += [
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cd_p .clk.eq(self.spi_clk), cd_p .rst.eq(self.spi_cs_n),
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cd_n .clk.eq(self.spi_clk), cd_n .rst.eq(self.spi_cs_n),
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cd_fw.clk.eq(self.spi_clk),
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cd_fr.clk.eq(self.spi_clk),
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]
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spi = SPIMode3Slave()
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m.submodules.spi = spi
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# RX bytes cross exiclk -> exi; TX bytes cross exi -> exiclk_n.
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# These are the ONLY crossings left, and each has a whole byte-time
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# (~296 ns at 27 MHz) of slack -- unlike the old design, where
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# bit-level MISO timing crossed a domain with a 37 ns budget.
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rx_fifo = AsyncFIFO(width=8, depth=self._rx_depth,
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w_domain="exififo_w", r_domain="sync")
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tx_fifo = AsyncFIFO(width=8, depth=self._tx_depth,
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w_domain="sync", r_domain="exififo_r")
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m.submodules.rx_fifo = rx_fifo
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m.submodules.tx_fifo = tx_fifo
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# ── Physical pins ↔ bit engine ───────────────────────────────────
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m.d.comb += [
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spi.spi_clk .eq(self.spi_clk),
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spi.spi_mosi.eq(self.spi_mosi),
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spi.spi_cs_n.eq(self.spi_cs_n),
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self.spi_miso.eq(spi.spi_miso),
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]
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# ── RX: every received byte → rx_fifo ────────────────────────────
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m.d.comb += [
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rx_fifo.w_data.eq(spi.rx_byte),
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rx_fifo.w_en .eq(spi.rx_valid),
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self.rx_data .eq(rx_fifo.r_data),
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self.rx_rdy .eq(rx_fifo.r_rdy),
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rx_fifo.r_en .eq(self.rx_en),
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]
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# ── TX: core pushes responses; the engine pops one per byte-time ──
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# The engine suppresses the pop during the protocol's turnaround byte
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# and drains stale bytes during the rest of the header, so no
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# CS-fall flush or slot-threshold logic is needed here any more.
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m.d.comb += [
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tx_fifo.w_data.eq(self.tx_data),
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tx_fifo.w_en .eq(self.tx_en),
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self.tx_rdy .eq(tx_fifo.w_rdy),
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spi.tx_byte .eq(tx_fifo.r_data),
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tx_fifo.r_en .eq(spi.tx_load),
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]
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# ── Transaction framing, in the slow domain ──────────────────────
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# CS is slow relative to `exi`, so a plain synchroniser is correct and
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# there is no longer any reason to detect it in a fast domain.
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cs_n_s = Signal(init=1)
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m.submodules.cs_sync = FFSynchronizer(self.spi_cs_n, cs_n_s,
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o_domain="sync", init=1)
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cs_n_prev = Signal(init=1)
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m.d.sync += cs_n_prev.eq(cs_n_s)
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m.d.comb += self.cs_active.eq(~cs_n_s)
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return m
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# ── Testbench ─────────────────────────────────────────────────────────────
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if __name__ == "__main__":
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import sys
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from amaranth.sim import Simulator, Period
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dut = ExiCapture()
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errors = []
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# SPI half-period in capture ticks. At 54 MHz capture / 27 MHz EXI the real
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# ratio is ~2; use 4 here for a clean, well-oversampled functional check.
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HALF = 4
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# No capture domain any more: the bit engine is clocked by the EXI
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# pin, so drive the SPI clock with real delays instead of ticks.
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HP = Period(MHz=54) * HALF
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async def spi_byte(ctx, mosi_val):
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"""Clock one SPI Mode 3 byte; return the assembled MISO byte."""
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miso = 0
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for bit in range(7, -1, -1):
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ctx.set(dut.spi_mosi, (mosi_val >> bit) & 1)
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ctx.set(dut.spi_clk, 0)
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await ctx.delay(HP * (HALF))
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miso = (miso << 1) | ctx.get(dut.spi_miso)
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ctx.set(dut.spi_clk, 1)
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await ctx.delay(HP * (HALF))
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return miso
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async def core_drain_rx(ctx, into):
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"""Pop one byte from the core RX side if available."""
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if ctx.get(dut.rx_rdy):
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into.append(ctx.get(dut.rx_data))
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ctx.set(dut.rx_en, 1)
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await ctx.tick("sync").repeat(1)
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ctx.set(dut.rx_en, 0)
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return True
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return False
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async def push_tx(ctx, b):
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ctx.set(dut.tx_data, b)
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ctx.set(dut.tx_en, 1)
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await ctx.tick("sync").repeat(1)
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ctx.set(dut.tx_en, 0)
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async def do_txn(ctx, hdr, responses, n_data, rx_seen):
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"""One EXI transaction: clock `hdr` bytes, model the clock-idle gap
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(drain rx + prefetch `responses` into tx_fifo), then clock `n_data`
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data bytes; return the MISO data bytes read."""
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ctx.set(dut.spi_cs_n, 0)
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ctx.set(dut.spi_clk, 1)
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await ctx.delay(HP * (HALF))
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for h in hdr:
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await spi_byte(ctx, h)
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for _ in range(20): # clock-idle gap
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await core_drain_rx(ctx, rx_seen)
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await ctx.tick("sync").repeat(1)
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for r in responses:
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await push_tx(ctx, r)
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await ctx.delay(HP * (2))
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miso = [await spi_byte(ctx, 0x00) for _ in range(n_data)]
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ctx.set(dut.spi_cs_n, 1)
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await ctx.delay(HP * (HALF))
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for _ in range(20): # drain data-phase dummies
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await core_drain_rx(ctx, rx_seen)
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await ctx.tick("sync").repeat(1)
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return miso
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async def testbench(ctx):
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rx_seen = []
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await ctx.delay(HP * (2))
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# ── T1: header + 2 data bytes read back ──────────────────────────
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miso = await do_txn(ctx, [0x12, 0x34], [0xA5, 0x5A], 2, rx_seen)
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print(f"T1 rx={[hex(b) for b in rx_seen[:2]]} MISO={[f'0x{b:02X}' for b in miso]}")
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if rx_seen[:2] != [0x12, 0x34]:
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errors.append(f"T1 header rx wrong: {rx_seen[:2]}")
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if miso != [0xA5, 0x5A]:
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errors.append(f"T1 MISO wrong: {[hex(b) for b in miso]}")
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# ── T2: prefetch over-push must NOT leak into the next transaction ─
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# Txn A pushes 2 responses but the GC clocks only 1 data byte, leaving
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# one stale byte in tx_fifo. Txn B must read its OWN fresh responses,
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# proving the CS-fall flush cleared the stale prefetch.
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rx_seen.clear()
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await do_txn(ctx, [0x12, 0x34], [0xA5, 0x5A], 1, rx_seen) # leaves 0x5A
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misoB = await do_txn(ctx, [0x12, 0x34], [0x11, 0x22], 2, rx_seen)
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print(f"T2 MISO after over-push: {[f'0x{b:02X}' for b in misoB]} (want 0x11 0x22)")
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if misoB != [0x11, 0x22]:
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errors.append(f"T2 flush failed — stale byte leaked: {[hex(b) for b in misoB]}")
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sim = Simulator(dut)
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sim.add_clock(Period(MHz=24), domain="sync")
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sim.add_testbench(testbench)
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with sim.write_vcd("ExiCapture.vcd"):
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sim.run()
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if errors:
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print("\nFAILURES:")
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for e in errors:
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print(" ", e)
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sys.exit(1)
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else:
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print("\nAll tests passed.")
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