Roflin 9a7eb54801 exi_j4: shared AND-merge helper + enumeration testbench ...

Factors the EXI_J4 pad merge out of synth.py so the synthesis path and the
test exercise the same code.  Verifies the device ID (04 02 02 00) enumerates
over SP1 with J4 idle, over J4 with SP1 idle, and over SP1 again afterwards,
plus a register read via J4 and the full cs_n truth table.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

2026-09-30 18:12:26 +00:00

..

__init__.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

bba_register_file.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

bba_top.py

fix(w5100): revert buffer base to 0x4000/0x6000 — IDM decodes only 15 bits

2026-09-20 18:56:38 +00:00

diagram.py

Adds diagrams.

2026-06-13 19:02:58 +02:00

eeprom_model.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

exi_capture.py

Add integrated UART UDP bring-up shell (socket 3) + capture critical-path fix

2026-08-02 14:36:47 +00:00

exi_j4.py

exi_j4: shared AND-merge helper + enumeration testbench

2026-09-30 18:12:26 +00:00

rx_frame_assembler.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

spi_mode3_slave.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

spram_arbiter.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

status_panel.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

synth.py

synth: optional EXI mirror on the J4 debug header (EXI_J4=1)

2026-09-30 17:54:24 +00:00

tx_frame_drain.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

uart_console.py

Added Uart.

2026-06-14 09:37:59 +02:00

uart_shell.py

Add integrated UART UDP bring-up shell (socket 3) + capture critical-path fix

2026-08-02 14:36:47 +00:00

w5100_parallel_master.py

fix(w5100): revert buffer base to 0x4000/0x6000 — IDM decodes only 15 bits

2026-09-20 18:56:38 +00:00

w5100_regdump.py

Add W5100 read-only register-dump probe (bring-up)

2026-09-20 15:03:44 +00:00

w5100_selftest.py

fix(w5100): unlock NETLCKR before writing GWR/SUBR/SHAR/SIPR (W5100S)

2026-09-20 14:51:33 +00:00

w5100_udptest.py

Hardware bring-up: first UDP packet transmitted and captured

2026-09-20 19:10:07 +00:00

w5500_spi_master.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00