Roflin
59948812f3
From the physical V2 bring-up session (2026-09-20): - exi_bba/w5100_selftest.py (NEW): standalone FPGA<->W5100 bus diagnostic. Clock-independent data-bus walk (direct-mode GAR0 read-back, all 8 lines) + MR software-reset self-clear (needs the 25 MHz crystal). Reports 4 verdicts on D6/D7 LEDs AND over UART (115200): GOOD / data-line-N / clock-dead / no-response. Boot wait is 85 ms (> the W5100S 60.3 ms init). On this board: GOOD -- bus + all 8 data lines + 25 MHz clock all verified (unlike V1's broken D3). - REVIEW.md / TODO.md: eFuse U13 OVLO is tied to GND, which on the TPS25961 selects the internal FIXED ~6 V overvoltage cutoff -- so it blocks the 12 V rail entirely (bench-confirmed: 12V_EXI=0, GC_ON=0, W5100 unpowered). FAB- BLOCKER for V2.1: fix with an OVLO divider (~1.1M/100k -> trip ~15 V). Bench workaround: lift U13 pin 2 (OVLO) off GND. Also closed the eFuse-placement, GND-via/3V3-zone, and CC-ESD TODO items. - hardware/re-bba-rb/exi_devid_spi.py (NEW): Pi hardware-SPI (~25 MHz) EXI device-ID host, companion to the bit-bang exi_devid_rpi.py. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
36 lines
589 B
Plaintext
36 lines
589 B
Plaintext
# Generated FPGA build artifacts (regenerate with: python -m exi_bba.synth)
|
|
build/
|
|
|
|
# Simulation waveforms (regenerate by running the testbenches)
|
|
*.vcd
|
|
|
|
# Python
|
|
__pycache__/
|
|
*.pyc
|
|
*.pyo
|
|
.venv/
|
|
venv/
|
|
|
|
# KiCad
|
|
fp-info-cache
|
|
*.bak
|
|
~*.lck
|
|
*-backups/
|
|
_autosave-*
|
|
.history/
|
|
hardware/re-bba-rb/gerbers
|
|
hardware/sp1_insert/gerbers
|
|
hardware/re-bba-rb/production
|
|
*-bom.csv
|
|
*-cpl.csv
|
|
*.rpt
|
|
# FT2232H EEPROM backup written by flash_ftdi_eeprom.py at runtime
|
|
hardware/re-bba-rb/eeprom-backup.bin
|
|
hardware/re-bba-rb/re-bba-rb-eeprom.bin
|
|
|
|
# Editor / OS cruft
|
|
.DS_Store
|
|
*.swp
|
|
.history/
|
|
build_w5100test/
|