Roflin
394b677c8f
Reverts the 0x8000/0xC000 change from162dbf7, which was WRONG and actively broke transmission. The W5100S datasheet pseudo-code quotes 0x8000 (TX) / 0xC000 (RX) for the memory blocks, but the PARALLEL/indirect (IDM) interface only decodes a 15-bit offset. Bench-proven with an address-aliasing probe: writing distinct values to each candidate base and reading them back showed 0xC000 and 0x4000 are the SAME cell (0xC000 & 0x7FFF == 0x4000) while 0x6000 holds its own value. Consequence of the bad base: every payload byte written to 0x9800+i aliased down onto 0x0000+i, landing on SHAR (0x09-0x0E) and SIPR (0x0F-0x12) and overwriting them with the payload. The chip then transmitted frames with a garbage source MAC/IP, which the peer NIC drops without counting -- the "SEND_OK but rx_packets=0" symptom, and the bogus SIPR0 readback (0x50 was literally payload byte 15, 'P'). The NETLCKR unlock from9c4bc7ais a genuine W5100S requirement and stays. Also: - w5100_udptest.py: self-contained configure+send+readback probe (and the address-aliasing probe that found this), reports over UART. - scripts/build-flash.sh: sweep N seeds and flash the best (capture timing is seed-dependent, so the sweep is mandatory). - scripts/uart-console.py: interactive UART console, plus --send/--read one-shot modes for scripting. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
246 lines
11 KiB
Python
246 lines
11 KiB
Python
"""Self-contained W5100S UDP send + register readback (bring-up diagnostic).
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One bitstream does EVERYTHING — reset, configure socket 3 for UDP, send a
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broadcast, then read back what the chip made of it — so there is no reflash gap
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and no "did the W5100 get reset in between?" ambiguity that made the read-only
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w5100_regdump probe inconclusive.
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It streams the verdict on the UART (115200 8N1):
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U: SIP=XX SSR=XX SIR=XX TRD=XXXX TWR=XXXX
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SIP SIPR0 read back. C0 (=192) => NETLCKR unlock worked and the network
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config actually took. 00 => the write was still being dropped.
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SSR Sn_SR after OPEN. 22 => SOCK_UDP, the socket really opened.
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00 => never opened (OPEN rejected) — SEND can then do nothing.
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SIR Sn_IR after SEND. bit4 (10) => SEND_OK, the chip completed the send.
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TRD/TWR Sn_TX_RD / Sn_TX_WR. TWR should equal the queued byte count;
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TRD catching up to TWR means the chip actually drained/transmitted it.
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TWR=0000 => nothing was ever queued.
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Everything is driven from a flat (addr, data) script executed over the indirect
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bus, so the whole configure+send is a table rather than a hand-rolled FSM.
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Build/flash: python -m exi_bba.w5100_udptest --flash
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"""
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from amaranth import *
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_A_MR, _A_AR0, _A_AR1, _A_DR = 0b00, 0b01, 0b10, 0b11
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_MR_IND, _MR_AI, _MR_RST = 0x01, 0x02, 0x80
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_SOCK = 3
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_SBASE = 0x0400 + _SOCK * 0x0100 # socket-3 register block = 0x0700
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_TXBUF = 0x8000 + _SOCK * 0x0800 # socket-3 TX buffer (W5100S) = 0x9800
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_PAYLEN = 32 # >= 18 so the frame clears 64B minimum
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# ── address-aliasing probe: distinct value to each candidate address ────────
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_CFG1 = [
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(0x4000, 0x11), (0x6000, 0x22), (0x8000, 0x33),
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(0x9800, 0x44), (0xC000, 0x55),
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]
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_CFG2 = [(0x0030, 0x66)]
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_SCRIPT = _CFG1 + _CFG2
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_N1 = len(_CFG1)
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# registers read back, in report order
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_READS = [("A40", 0x4000), ("A60", 0x6000), ("A80", 0x8000),
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("A98", 0x9800), ("AC0", 0xC000), ("A30", 0x0030)]
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class W5100UdpTest(Elaboratable):
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def __init__(self, *, strobe_cycles=3, rst_cycles=48_000,
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boot_cycles=2_040_000, settle_cycles=240_000):
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self._strobe = strobe_cycles
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self._rst = rst_cycles
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self._boot = boot_cycles # >= 60.3 ms W5100S init
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self._settle = settle_cycles # ~10 ms waits after OPEN and after SEND
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self.bus_addr = Signal(2)
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self.bus_data_o = Signal(8); self.bus_data_oe = Signal()
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self.bus_data_i = Signal(8)
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self.cs_n = Signal(init=1); self.rd_n = Signal(init=1)
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self.wr_n = Signal(init=1); self.rst_n = Signal(init=1)
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self.uart_tx = Signal(init=1)
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self.vals = Array([Signal(8, name=f"v{i}") for i in range(len(_READS))])
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self.done = Signal()
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def elaborate(self, platform):
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m = Module()
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S = self._strobe
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# ── bus engine ───────────────────────────────────────────────────────
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go=Signal(); rw=Signal(); ba=Signal(2); wd=Signal(8); rdv=Signal(8)
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bdone=Signal(); bctr=Signal(range(S+2)); rw_r=Signal()
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a_o=Signal(2); d_o=Signal(8); d_oe=Signal()
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cs=Signal(init=1); rdn=Signal(init=1); wrn=Signal(init=1); rstn=Signal(init=1)
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m.d.comb += [self.bus_addr.eq(a_o), self.bus_data_o.eq(d_o),
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self.bus_data_oe.eq(d_oe), self.cs_n.eq(cs),
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self.rd_n.eq(rdn), self.wr_n.eq(wrn), self.rst_n.eq(rstn)]
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m.d.sync += bdone.eq(0)
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with m.FSM(domain="sync", name="bus"):
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with m.State("IDLE"):
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m.d.sync += [cs.eq(1), rdn.eq(1), wrn.eq(1), d_oe.eq(0)]
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with m.If(go):
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m.d.sync += [a_o.eq(ba), rw_r.eq(rw), cs.eq(0), bctr.eq(0)]
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with m.If(rw):
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m.d.sync += [d_o.eq(wd), d_oe.eq(1), wrn.eq(0)]
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with m.Else():
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m.d.sync += rdn.eq(0)
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m.next="STROBE"
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with m.State("STROBE"):
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m.d.sync += bctr.eq(bctr+1)
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with m.If(bctr == S-1):
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with m.If(~rw_r): m.d.sync += rdv.eq(self.bus_data_i)
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m.d.sync += [rdn.eq(1), wrn.eq(1)]
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m.next="FINISH"
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with m.State("FINISH"):
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m.d.sync += [cs.eq(1), d_oe.eq(0), bdone.eq(1)]
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m.next="IDLE"
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m.d.comb += [go.eq(0), rw.eq(0), ba.eq(0), wd.eq(0)]
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def bw(a,d): m.d.comb += [go.eq(1), rw.eq(1), ba.eq(a), wd.eq(d)]
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def br(a): m.d.comb += [go.eq(1), rw.eq(0), ba.eq(a)]
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saddr = Array([Const(a,16) for a,_ in _SCRIPT])
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sdata = Array([Const(d,8) for _,d in _SCRIPT])
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raddr = Array([Const(a,16) for _,a in _READS])
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si = Signal(range(len(_SCRIPT)+1))
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ri = Signal(range(len(_READS)+1))
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ctr = Signal(range(max(self._rst,self._boot,self._settle)+2))
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send_phase = Signal() # 0 = running CFG1, 1 = running CFG2
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with m.FSM(domain="sync", name="seq"):
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with m.State("RST"):
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m.d.sync += [rstn.eq(0), ctr.eq(ctr+1)]
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with m.If(ctr == self._rst-1):
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m.d.sync += ctr.eq(0); m.next="BOOT"
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with m.State("BOOT"):
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m.d.sync += [rstn.eq(1), ctr.eq(ctr+1)]
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with m.If(ctr == self._boot-1):
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m.d.sync += ctr.eq(0); m.next="MRMODE"
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with m.State("MRMODE"): # MR = indirect + AI
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bw(_A_MR, _MR_IND | _MR_AI); m.next="MRMODE_W"
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with m.State("MRMODE_W"):
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with m.If(bdone): m.d.sync += si.eq(0); m.next="W_AR0"
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# generic script executor: indirect write saddr[si] = sdata[si]
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with m.State("W_AR0"):
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bw(_A_AR0, saddr[si][8:16]); m.next="W_AR0_W"
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with m.State("W_AR0_W"):
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with m.If(bdone): m.next="W_AR1"
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with m.State("W_AR1"):
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bw(_A_AR1, saddr[si][0:8]); m.next="W_AR1_W"
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with m.State("W_AR1_W"):
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with m.If(bdone): m.next="W_DR"
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with m.State("W_DR"):
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bw(_A_DR, sdata[si]); m.next="W_DR_W"
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with m.State("W_DR_W"):
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with m.If(bdone):
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m.d.sync += si.eq(si+1)
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with m.If((si+1 == _N1) & ~send_phase):
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m.d.sync += [ctr.eq(0), send_phase.eq(1)]
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m.next="SETTLE1" # let OPEN take effect
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with m.Elif(si+1 == len(_SCRIPT)):
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m.d.sync += ctr.eq(0); m.next="SETTLE2" # let SEND finish
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with m.Else():
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m.next="W_AR0"
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with m.State("SETTLE1"):
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m.d.sync += ctr.eq(ctr+1)
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with m.If(ctr == self._settle-1):
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m.d.sync += ctr.eq(0); m.next="W_AR0" # continue with CFG2
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with m.State("SETTLE2"):
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m.d.sync += ctr.eq(ctr+1)
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with m.If(ctr == self._settle-1):
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m.d.sync += [ctr.eq(0), ri.eq(0)]; m.next="R_AR0"
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# generic readback: indirect read raddr[ri] -> vals[ri]
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with m.State("R_AR0"):
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bw(_A_AR0, raddr[ri][8:16]); m.next="R_AR0_W"
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with m.State("R_AR0_W"):
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with m.If(bdone): m.next="R_AR1"
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with m.State("R_AR1"):
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bw(_A_AR1, raddr[ri][0:8]); m.next="R_AR1_W"
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with m.State("R_AR1_W"):
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with m.If(bdone): m.next="R_DR"
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with m.State("R_DR"):
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br(_A_DR); m.next="R_DR_W"
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with m.State("R_DR_W"):
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with m.If(bdone):
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m.d.sync += self.vals[ri].eq(rdv)
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with m.If(ri == len(_READS)-1):
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m.next="DONE"
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with m.Else():
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m.d.sync += ri.eq(ri+1); m.next="R_AR0"
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with m.State("DONE"):
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m.d.comb += self.done.eq(1)
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# ── UART report ──────────────────────────────────────────────────────
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DIV = round(24_000_000/115_200)
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parts = b"U:"; pos={}
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for name,_ in _READS:
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parts += b" "+name.encode()+b"="; pos[name]=len(parts); parts += b"00"
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parts += b"\r\n"
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tmpl=list(parts); MSGLEN=len(tmpl)
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rom=Array([Const(b,8) for b in tmpl])
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def hexch(n): return Mux(n<10, 0x30+n, 0x37+n)
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cur=Signal(8); uidx=Signal(range(MSGLEN+1))
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m.d.comb += cur.eq(rom[uidx])
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with m.Switch(uidx):
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for i,(name,_) in enumerate(_READS):
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p=pos[name]
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with m.Case(p): m.d.comb += cur.eq(hexch(self.vals[i][4:8]))
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with m.Case(p+1): m.d.comb += cur.eq(hexch(self.vals[i][0:4]))
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shift=Signal(10, init=0x3FF); nb=Signal(range(11)); bd=Signal(range(DIV))
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gap=Signal(range(DIV*30+1))
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m.d.comb += self.uart_tx.eq(shift[0])
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with m.FSM(domain="sync", name="uart"):
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with m.State("IDLE"):
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with m.If(self.done): m.d.sync += uidx.eq(0); m.next="LOAD"
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with m.State("LOAD"):
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with m.If(uidx==MSGLEN):
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m.d.sync += gap.eq(DIV*30); m.next="GAP"
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with m.Else():
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m.d.sync += [shift.eq(Cat(C(0,1),cur,C(1,1))), nb.eq(10), bd.eq(DIV-1)]
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m.next="SHIFT"
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with m.State("SHIFT"):
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with m.If(bd==0):
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m.d.sync += bd.eq(DIV-1)
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with m.If(nb==1):
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m.d.sync += uidx.eq(uidx+1); m.next="LOAD"
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with m.Else():
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m.d.sync += [nb.eq(nb-1), shift.eq(Cat(shift[1:],C(1,1)))]
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with m.Else():
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m.d.sync += bd.eq(bd-1)
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with m.State("GAP"):
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m.d.sync += gap.eq(gap-1)
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with m.If(gap==0): m.d.sync += uidx.eq(0); m.next="LOAD"
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return m
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class W5100UdpTestTop(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.domains += ClockDomain("sync")
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m.submodules.hfosc = Instance("SB_HFOSC", p_CLKHF_DIV="0b01",
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i_CLKHFEN=Const(1,1), i_CLKHFPU=Const(1,1), o_CLKHF=ClockSignal("sync"))
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m.submodules.dut = dut = W5100UdpTest()
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w = platform.request("w5100", 0); u = platform.request("uart", 0)
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m.d.comb += [
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w.addr.o.eq(dut.bus_addr), w.data.o.eq(dut.bus_data_o),
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w.data.oe.eq(dut.bus_data_oe), dut.bus_data_i.eq(w.data.i),
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w.cs_n.o.eq(dut.cs_n), w.rd_n.o.eq(dut.rd_n),
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w.wr_n.o.eq(dut.wr_n), w.rst_n.o.eq(dut.rst_n),
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u.tx.o.eq(dut.uart_tx),
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]
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return m
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if __name__ == "__main__":
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import sys
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if "--build" in sys.argv or "--flash" in sys.argv:
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from exi_bba.synth import IceBreakerPlatform
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IceBreakerPlatform().build(W5100UdpTestTop(), do_program="--flash" in sys.argv,
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name="w5100_udptest", build_dir="build_w5100test")
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print("[built] build_w5100test/w5100_udptest.bin")
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raise SystemExit(0)
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print(f"script={len(_SCRIPT)} writes (CFG1={_N1}), payload={_PAYLEN}B at {_TXBUF:#06x}")
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print("use --build or --flash (hardware probe)")
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