Dennis Brentjes
27 lines
1.3 KiB
Plaintext
27 lines
1.3 KiB
Plaintext
(version 1)
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# SP1 edge-connector (J3): the gold fingers must reach the board edge to make
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# contact in the GameCube slot, so copper-to-edge clearance is intentionally
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# relaxed for this footprint only. This is by design, not a defect.
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# Test BOTH items because the violated pair is (Edge.Cuts segment of J3) vs (pad
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# of J3) - the edge segment is item A, the pad is item B.
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(rule "SP1 gold fingers - allow copper to board edge"
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(condition "A.memberOfFootprint('J3') || B.memberOfFootprint('J3')")
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(constraint edge_clearance (min -0.5mm)))
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# Power-integrity: flag any power-rail track narrower than its netclass width.
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# A netclass "track width" is only the DEFAULT for new routing - KiCad does NOT
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# enforce it - so without these rules an under-width power trace passes DRC
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# silently. These make DRC surface every thin power segment so they don't have to
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# be found by eye. Severity is "warning" (not error) so an unavoidable neck into a
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# fine-pitch pin is flagged for review but never blocks fab export.
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(rule "Power rail minimum width (0.3mm)"
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(severity warning)
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(condition "A.NetClass == 'Power'")
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(constraint track_width (min 0.3mm)))
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(rule "Low-current power rail minimum width (0.25mm)"
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(severity warning)
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(condition "A.NetClass == 'PowerLV'")
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(constraint track_width (min 0.25mm)))
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