Roflin
59948812f3
From the physical V2 bring-up session (2026-09-20): - exi_bba/w5100_selftest.py (NEW): standalone FPGA<->W5100 bus diagnostic. Clock-independent data-bus walk (direct-mode GAR0 read-back, all 8 lines) + MR software-reset self-clear (needs the 25 MHz crystal). Reports 4 verdicts on D6/D7 LEDs AND over UART (115200): GOOD / data-line-N / clock-dead / no-response. Boot wait is 85 ms (> the W5100S 60.3 ms init). On this board: GOOD -- bus + all 8 data lines + 25 MHz clock all verified (unlike V1's broken D3). - REVIEW.md / TODO.md: eFuse U13 OVLO is tied to GND, which on the TPS25961 selects the internal FIXED ~6 V overvoltage cutoff -- so it blocks the 12 V rail entirely (bench-confirmed: 12V_EXI=0, GC_ON=0, W5100 unpowered). FAB- BLOCKER for V2.1: fix with an OVLO divider (~1.1M/100k -> trip ~15 V). Bench workaround: lift U13 pin 2 (OVLO) off GND. Also closed the eFuse-placement, GND-via/3V3-zone, and CC-ESD TODO items. - hardware/re-bba-rb/exi_devid_spi.py (NEW): Pi hardware-SPI (~25 MHz) EXI device-ID host, companion to the bit-bang exi_devid_rpi.py. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
66 lines
3.3 KiB
Python
66 lines
3.3 KiB
Python
#!/usr/bin/env python3
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"""EXI device-ID query over the Pi's HARDWARE SPI (spidev) — a near-full-speed
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(~25 MHz, close to the GameCube's real ~27 MHz EXI clock) companion to the
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bit-bang exi_devid_rpi.py.
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Use bit-bang (exi_devid_rpi.py) for a slow logic smoke test; use THIS to prove
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the FPGA's SPI Mode-3 capture front-end also samples cleanly *at rate* without a
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GameCube. The Pi 4 SPI SCK is core_clk/even-divisor, so a 27 MHz request lands
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on ~25 MHz — comfortably inside the design's 54 MHz 2x oversampling (and a hair
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more margin than the real 27 MHz). Do NOT push past ~27 MHz: the capture domain
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only closes ~49-58 MHz across seeds, so >~27 MHz input under-samples.
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The FPGA prefetches the reply during a clock-IDLE gap between the header and the
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data bytes (the GC pauses the clock there), so CS must stay LOW across that gap.
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spidev toggles CS per call, so we park SPI0's hardware CS on BCM7 (unused) and
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drive the real CS manually on BCM8. Pi config (then reboot):
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/boot/firmware/config.txt: dtoverlay=spi0-1cs,cs0_pin=7
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(That frees BCM8 and puts the unused hw CE0 on BCM7. To go back to the bit-bang
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script, remove that line + reboot so BCM9/10/11 return to plain GPIO.)
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Wiring (Pi -> FPGA EXI, all 3.3 V, shared GND) — identical to the bit-bang one:
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SCLK BCM11 (pin 23) -> EXI CLK (FPGA 44)
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MOSI BCM10 (pin 19) -> EXI MOSI (FPGA 4)
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MISO BCM9 (pin 21) <- EXI MISO (FPGA 3)
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CS BCM8 (pin 24) -> EXI CS (FPGA 45) [held low manually across the txn]
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GND (pin 25) <-> GND
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Run: sudo python3 exi_devid_spi.py [speed_hz] [gap_us]
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"""
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import sys, time
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import spidev
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try:
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import RPi.GPIO as GPIO
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except ImportError:
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raise SystemExit("needs RPi.GPIO -> sudo apt install python3-rpi.gpio")
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SPEED = int(sys.argv[1]) if len(sys.argv) > 1 else 27_000_000 # ~25 MHz actual (core/10)
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GAP_US = int(sys.argv[2]) if len(sys.argv) > 2 else 50 # header->data prefetch gap
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CS = 8 # BCM8 manual chip-select (hardware CE0 parked on BCM7 by the overlay)
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spi = spidev.SpiDev()
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spi.open(0, 0)
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spi.mode = 0b11 # SPI Mode 3: CPOL=1, CPHA=1 (EXI CLK idles high)
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spi.max_speed_hz = SPEED
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GPIO.setmode(GPIO.BCM)
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GPIO.setup(CS, GPIO.OUT, initial=1) # CS idle high
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GPIO.output(CS, 0) # assert CS (active low) for the whole transaction
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spi.xfer2([0x00, 0x03]) # header: read, addr[12:0]=0, len-1=3 (4 bytes)
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time.sleep(GAP_US / 1e6) # clock-idle gap -> FPGA prefetches the reply
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resp = spi.xfer2([0x00] * 6) # clock read bytes; MISO carries the response
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GPIO.output(CS, 1) # deassert CS
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spi.close(); GPIO.cleanup()
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print(f"SPI mode 3, {SPEED/1e6:.1f} MHz requested (actual ~= core/even-divisor, ~25 MHz), "
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f"header->data gap {GAP_US} us")
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print("read bytes:", " ".join("%02x" % b for b in resp))
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want = [0x04, 0x02, 0x02, 0x00]
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if any(resp[i:i + 4] == want for i in range(len(resp) - 3)):
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print("EXI device-ID 04 02 02 00 -> FOUND. Capture path works at ~full EXI rate!")
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else:
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print("device-ID not found. If the slow bit-bang test (exi_devid_rpi.py) PASSES "
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"but this fails, the front-end is marginal at rate on the flashed seed -> "
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"reflash the BEST --seeds bitstream, and/or raise the gap (arg2) or lower "
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"the speed (arg1). Otherwise check wiring/GND and that the FPGA is running.")
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