Dennis Brentjes
313 lines
12 KiB
Python
313 lines
12 KiB
Python
"""RX frame assembler — sync domain (24 MHz).
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Receives raw ethernet frames from W5500SPIMaster and writes them into the SPRAM
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ring buffer in MX98730EC format.
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Ring buffer layout (SPRAM byte addresses)
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------------------------------------------
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0x0100–0x0FFF 15 pages × 256 bytes = 3840 bytes
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Pages 0x01–0x0F; page 0x00 is reserved.
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Page wrap: after 0x0F → 0x01 (skip 0x00).
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Frame descriptor (4 bytes at page start)
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-----------------------------------------------
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Byte 0: LRPS (last received packet status) — 0x00
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Byte 1: 0x00
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Byte 2: total_length[15:8] (big-endian; includes 4 descriptor bytes)
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Byte 3: total_length[7:0]
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Bytes 4+: raw ethernet frame
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Write sequence
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--------------
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1. Issue 4 SPRAM writes of 0x00 (placeholder descriptor).
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2. For each byte received from W5500, issue one SPRAM write.
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3. After EOF: rewrite descriptor bytes 2 and 3 with actual length.
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4. Advance RWP, push to rx_wptr FIFO, pulse rx_irq.
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"""
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from amaranth import *
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__all__ = ["RXFrameAssembler"]
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_RX_PAGE_FIRST = 0x01
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_RX_PAGE_LAST = 0x0F
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_PAGES_TOTAL = _RX_PAGE_LAST - _RX_PAGE_FIRST + 1 # 15
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class RXFrameAssembler(Elaboratable):
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"""Writes incoming ethernet frames into the SPRAM ring buffer.
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W5500 streaming interface (sync domain)
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----------------------------------------
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rx_data / rx_valid / rx_ready : byte stream
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rx_sof / rx_eof : frame delimiters (same cycle as rx_valid)
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SPRAM write interface (to SPRAMArbiter, sync domain)
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-----------------------------------------------------
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eth_wr_addr / eth_wr_data / eth_wr_valid / eth_wr_ready
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CDC outputs (wired by BBATop)
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-----------------------------
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rx_wptr_w_data / rx_wptr_w_en / rx_wptr_w_rdy
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rx_irq : 1-cycle pulse → PulseSynchronizer input
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rx_enabled : controlled by NCRA SR bit (from BBARegisterFile)
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"""
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def __init__(self):
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# W5500 stream in
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self.rx_data = Signal(8)
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self.rx_valid = Signal()
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self.rx_ready = Signal()
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self.rx_sof = Signal()
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self.rx_eof = Signal()
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# SPRAM write out
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self.eth_wr_addr = Signal(16)
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self.eth_wr_data = Signal(8)
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self.eth_wr_valid = Signal()
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self.eth_wr_ready = Signal()
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# RWP FIFO write-side (sync→exi)
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self.rx_wptr_w_data = Signal(8)
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self.rx_wptr_w_en = Signal()
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self.rx_wptr_w_rdy = Signal()
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# rx_irq pulse (→ PulseSynchronizer)
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self.rx_irq = Signal()
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# RX gate from NCRA SR bit
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self.rx_enabled = Signal()
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def elaborate(self, platform):
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m = Module()
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# ── Ring-buffer state ─────────────────────────────────────────────
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rwp = Signal(8, init=_RX_PAGE_FIRST) # current RX write page (1–15)
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# Write address within current frame
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wr_addr = Signal(16)
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# Number of frame data bytes received
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data_ctr = Signal(12)
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# Total length = data_ctr + 4
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total_len = Signal(12)
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# Descriptor base (rwp*256) — saved when frame starts
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desc_base = Signal(16)
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# Placeholder descriptor byte counter (0..3)
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desc_ctr = Signal(2)
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# Number of pages consumed by this frame (rounded up)
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pages_used = Signal(5)
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# Default: no pulses
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m.d.sync += self.rx_irq.eq(0)
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m.d.sync += self.rx_wptr_w_en.eq(0)
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# Combinatorial outputs
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m.d.comb += total_len.eq(data_ctr + 4)
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with m.FSM(domain="sync", name="rx_fsm"):
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with m.State("IDLE"):
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m.d.comb += self.rx_ready.eq(0)
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m.d.sync += self.eth_wr_valid.eq(0)
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with m.If(self.rx_valid & self.rx_sof & self.rx_enabled):
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frame_base = Signal(16)
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m.d.comb += frame_base.eq(Cat(Const(0, 8), rwp))
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m.d.sync += desc_base.eq(frame_base)
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m.d.sync += wr_addr.eq(frame_base)
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m.d.sync += data_ctr.eq(0)
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m.d.sync += desc_ctr.eq(0)
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m.next = "WRITE_PLACEHOLDER"
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with m.State("WRITE_PLACEHOLDER"):
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# Write 4 bytes of 0x00 as placeholder descriptor
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m.d.sync += self.eth_wr_addr.eq(wr_addr)
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m.d.sync += self.eth_wr_data.eq(0x00)
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m.d.sync += self.eth_wr_valid.eq(1)
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with m.If(self.eth_wr_ready):
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m.d.sync += wr_addr.eq(wr_addr + 1)
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with m.If(desc_ctr == 3):
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m.d.sync += self.eth_wr_valid.eq(0)
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m.next = "RECV_AND_WRITE"
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with m.Else():
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m.d.sync += desc_ctr.eq(desc_ctr + 1)
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with m.State("RECV_AND_WRITE"):
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# Accept bytes from W5500 and write each to SPRAM immediately
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m.d.comb += self.rx_ready.eq(~self.eth_wr_valid | self.eth_wr_ready)
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with m.If(self.rx_valid & (~self.eth_wr_valid | self.eth_wr_ready)):
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m.d.sync += self.eth_wr_addr.eq(wr_addr)
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m.d.sync += self.eth_wr_data.eq(self.rx_data)
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m.d.sync += self.eth_wr_valid.eq(1)
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m.d.sync += wr_addr.eq(wr_addr + 1)
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m.d.sync += data_ctr.eq(data_ctr + 1)
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with m.If(self.rx_eof):
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m.next = "WAIT_LAST_WRITE"
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with m.Elif(self.eth_wr_valid & self.eth_wr_ready):
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m.d.sync += self.eth_wr_valid.eq(0)
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with m.State("WAIT_LAST_WRITE"):
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# Wait for the last data byte write to be accepted
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with m.If(~self.eth_wr_valid | self.eth_wr_ready):
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m.d.sync += self.eth_wr_valid.eq(0)
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# Compute pages used: ceil((data_ctr + 4) / 256)
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# = (total_len + 255) >> 8 = total_len[11:8] + (total_len[7:0] != 0)
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m.d.sync += pages_used.eq(total_len[8:12] + (total_len[:8] != 0))
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m.next = "WRITE_LEN_HI"
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with m.State("WRITE_LEN_HI"):
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# Overwrite descriptor byte 2 with total_len[15:8]
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m.d.sync += self.eth_wr_addr.eq(desc_base + 2)
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m.d.sync += self.eth_wr_data.eq(total_len[8:12])
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m.d.sync += self.eth_wr_valid.eq(1)
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with m.If(self.eth_wr_ready):
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m.d.sync += self.eth_wr_valid.eq(0)
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m.next = "WRITE_LEN_LO"
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with m.State("WRITE_LEN_LO"):
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# Overwrite descriptor byte 3 with total_len[7:0]
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m.d.sync += self.eth_wr_addr.eq(desc_base + 3)
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m.d.sync += self.eth_wr_data.eq(total_len[:8])
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m.d.sync += self.eth_wr_valid.eq(1)
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with m.If(self.eth_wr_ready):
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m.d.sync += self.eth_wr_valid.eq(0)
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m.next = "ADVANCE_RWP"
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with m.State("ADVANCE_RWP"):
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# next_rwp = ((rwp - 1 + pages_used) % 15) + 1
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next_rwp_raw = Signal(8)
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m.d.comb += next_rwp_raw.eq(rwp + pages_used)
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with m.If(next_rwp_raw > _RX_PAGE_LAST):
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m.d.sync += rwp.eq(next_rwp_raw - _PAGES_TOTAL)
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with m.Else():
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m.d.sync += rwp.eq(next_rwp_raw)
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m.next = "PUSH_WPT"
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with m.State("PUSH_WPT"):
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with m.If(self.rx_wptr_w_rdy):
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m.d.sync += self.rx_wptr_w_data.eq(rwp)
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m.d.sync += self.rx_wptr_w_en.eq(1)
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m.d.sync += self.rx_irq.eq(1)
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m.next = "IDLE"
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return m
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# ── Testbench ─────────────────────────────────────────────────────────────
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if __name__ == "__main__":
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import sys
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from amaranth.sim import Simulator, Period
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dut = RXFrameAssembler()
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errors = []
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# Track all SPRAM writes issued by the DUT
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spram_writes = []
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async def testbench(ctx):
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# Setup: acknowledge all SPRAM writes immediately
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ctx.set(dut.eth_wr_ready, 1)
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ctx.set(dut.rx_wptr_w_rdy, 1)
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ctx.set(dut.rx_enabled, 1)
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await ctx.tick("sync").repeat(2)
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# ── T1: 10-byte frame → pages_used=1, rwp advances 1→2 ──────────────
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# Send SOF + first byte
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frame = [0xAA, 0xBB, 0xCC, 0xDD, 0x08, 0x00, 0x45, 0x00, 0x00, 0x01]
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ctx.set(dut.rx_data, frame[0])
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ctx.set(dut.rx_valid, 1)
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ctx.set(dut.rx_sof, 1)
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await ctx.tick("sync").repeat(1)
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ctx.set(dut.rx_sof, 0)
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for i, b in enumerate(frame[1:], start=1):
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ctx.set(dut.rx_data, b)
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ctx.set(dut.rx_eof, 1 if i == len(frame) - 1 else 0)
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await ctx.tick("sync").repeat(1)
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ctx.set(dut.rx_valid, 0)
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ctx.set(dut.rx_eof, 0)
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# Poll for up to 30 ticks until rx_irq pulses (1-cycle pulse)
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t1_irq_seen = False
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t1_wptr_d = 0
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for _ in range(30):
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await ctx.tick("sync").repeat(1)
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if ctx.get(dut.rx_irq):
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t1_irq_seen = True
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t1_wptr_d = ctx.get(dut.rx_wptr_w_data)
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break
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print(f"T1 rx_irq_seen={t1_irq_seen} wptr_data=0x{t1_wptr_d:02X}")
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if not t1_irq_seen:
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errors.append("T1: rx_irq never pulsed")
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if t1_wptr_d != 2:
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errors.append(f"T1: rwp should be 2 (page 1→2), got {t1_wptr_d}")
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await ctx.tick("sync").repeat(4)
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# ── T2: Send a second frame; verify rwp advances further ────────────
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frame2 = [0x11, 0x22, 0x33, 0x44, 0x55, 0x66]
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ctx.set(dut.rx_data, frame2[0])
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ctx.set(dut.rx_valid, 1)
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ctx.set(dut.rx_sof, 1)
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await ctx.tick("sync").repeat(1)
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ctx.set(dut.rx_sof, 0)
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for i, b in enumerate(frame2[1:], start=1):
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ctx.set(dut.rx_data, b)
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ctx.set(dut.rx_eof, 1 if i == len(frame2) - 1 else 0)
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await ctx.tick("sync").repeat(1)
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ctx.set(dut.rx_valid, 0)
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ctx.set(dut.rx_eof, 0)
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t2_irq_seen = False
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t2_wptr_d = 0
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for _ in range(30):
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await ctx.tick("sync").repeat(1)
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if ctx.get(dut.rx_irq):
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t2_irq_seen = True
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t2_wptr_d = ctx.get(dut.rx_wptr_w_data)
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break
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print(f"T2 rx_irq_seen={t2_irq_seen} wptr_data=0x{t2_wptr_d:02X}")
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if not t2_irq_seen:
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errors.append("T2: rx_irq never pulsed after second frame")
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if t2_wptr_d != 3:
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errors.append(f"T2: rwp should be 3 (page 2→3), got {t2_wptr_d}")
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# ── T3: RX disabled — SOF must be ignored ──────────────────────────
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ctx.set(dut.rx_enabled, 0)
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ctx.set(dut.rx_data, 0xDE)
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ctx.set(dut.rx_valid, 1)
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ctx.set(dut.rx_sof, 1)
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await ctx.tick("sync").repeat(4)
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ctx.set(dut.rx_valid, 0)
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ctx.set(dut.rx_sof, 0)
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# No SPRAM write should have been issued
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wr_valid = ctx.get(dut.eth_wr_valid)
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if wr_valid:
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errors.append("T3: SPRAM write issued while rx_enabled=0")
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print(f"T3 rx disabled: eth_wr_valid={wr_valid} (expected 0)")
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sim = Simulator(dut)
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sim.add_clock(Period(MHz=24), domain="sync")
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sim.add_testbench(testbench)
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with sim.write_vcd("RXFrameAssembler.vcd"):
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sim.run()
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if errors:
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print("\nFAILURES:")
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for e in errors:
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print(" ", e)
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sys.exit(1)
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else:
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print("\nAll tests passed.")
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