Dennis Brentjes
761 lines
33 KiB
Python
761 lines
33 KiB
Python
"""W5500 SPI master — sync domain (24 MHz).
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SPI Mode 0 (CPOL=0, CPHA=0): CLK idles LOW, data captured on rising edge.
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SCK = 12 MHz: the sync domain is 24 MHz and the bit engine toggles SCK via a
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clock-enable (sync ÷ 2).
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W5500 frame format
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------------------
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Byte 0–1 Address (16-bit big-endian)
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Byte 2 Control: [7:3]=BSB [2]=R/W [1:0]=OM
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Byte 3+ Data
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BSB values used here:
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0b00000 Common registers
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0b00001 Socket 0 registers
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0b00010 Socket 0 TX buffer
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0b00011 Socket 0 RX buffer
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After NCRA reset the driver issues the W5500 init sequence (MR reset, SHAR,
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S0_MR MACRAW, S0_CR OPEN, S0_IMR).
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The module provides:
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- A streaming TX interface (tx_data/tx_valid/tx_ready + sof/eof framing)
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- A streaming RX interface (rx_data/rx_valid/rx_ready + sof/eof)
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- init_req / init_done for the NCRA-triggered init sequence
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- MAC source address shadow input (par[0..5]) for SHAR programming
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"""
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from amaranth import *
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__all__ = ["W5500SPIMaster"]
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# W5500 register addresses. The 16-bit address is the OFFSET WITHIN A BLOCK;
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# the block is selected by the BSB field of the control byte (see _CTRL_*),
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# NOT by the address. So socket-0 registers use small offsets with BSB=1.
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_W5500_MR = 0x0000 # Mode register (common block)
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_W5500_SHAR = 0x0009 # Source MAC, 6 bytes (common block)
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_W5500_S0_MR = 0x0000 # Socket 0 Mode (socket-0 block)
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_W5500_S0_CR = 0x0001 # Socket 0 Command
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_W5500_S0_IR = 0x0002 # Socket 0 Interrupt
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_W5500_S0_RXBUF_SIZE = 0x001E # Socket 0 RX buffer size
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_W5500_S0_TXBUF_SIZE = 0x001F # Socket 0 TX buffer size
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_W5500_S0_TX_FSR = 0x0020 # Socket 0 TX Free Size (2 bytes)
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_W5500_S0_TX_WR = 0x0024 # Socket 0 TX Write Pointer
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_W5500_S0_RX_RSR = 0x0026 # Socket 0 RX Received Size (2 bytes)
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_W5500_S0_RX_RD = 0x0028 # Socket 0 RX Read Pointer
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_W5500_S0_IMR = 0x002C # Socket 0 Interrupt Mask
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# Control byte = (BSB << 3) | (RWB << 2) | OM.
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# RWB: 1=write 0=read. OM=00 → Variable Data Mode (CS frames the length).
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# BSB: 0=common, 1=socket0 reg, 2=socket0 TX buffer, 3=socket0 RX buffer.
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_CTRL_WR_COMMON = (0 << 3) | (1 << 2) # 0x04
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_CTRL_WR_S0REG = (1 << 3) | (1 << 2) # 0x0C
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_CTRL_RD_S0REG = (1 << 3) | (0 << 2) # 0x08
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_CTRL_WR_S0TX = (2 << 3) | (1 << 2) # 0x14
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_CTRL_RD_S0RX = (3 << 3) | (0 << 2) # 0x18
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class W5500SPIMaster(Elaboratable):
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"""W5500 SPI master in the sync clock domain.
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Physical SPI pins
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-----------------
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spi_clk / spi_mosi / spi_miso / spi_cs_n : to W5500
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w5500_int_n : W5500 INT_N input (active low)
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w5500_rst_n : W5500 hardware reset (active low)
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Init interface (from BBARegisterFile / BBATop)
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----------------------------------------------
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init_req : pulse to trigger the W5500 init sequence
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init_done : pulse when init sequence completes
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par : 6-byte MAC address (sampled at init_req)
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TX streaming interface (from TXFrameDrain, sync domain)
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-------------------------------------------------------
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tx_data / tx_valid / tx_ready : byte stream
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tx_sof / tx_eof : frame delimiters on the same cycle as tx_valid
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RX streaming interface (to RXFrameAssembler, sync domain)
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----------------------------------------------------------
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rx_data / rx_valid / rx_ready : byte stream
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rx_sof / rx_eof : frame delimiters
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"""
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def __init__(self, clk_div=1, reset_cycles=24000):
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# MR-reset settle wait (in sync cycles). ~1 ms; the testbench
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# overrides with a small value for fast simulation.
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self._reset_cycles = reset_cycles
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# SPI SCK = sync_clock / (2 * clk_div). clk_div=1 → full rate (SCK =
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# sync/2): at the 24 MHz slow domain that is 12 MHz SCK (~12 Mbit/s),
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# which comfortably exceeds real-world GC BBA TCP throughput. The W5500
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# tolerates up to 80 MHz SCK, so the divider exists only as a safety
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# knob for board-level signal-integrity issues, not a functional need.
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self._clk_div = clk_div
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# Physical SPI
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self.spi_clk = Signal()
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self.spi_mosi = Signal()
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self.spi_miso = Signal()
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self.spi_cs_n = Signal(init=1)
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self.w5500_int_n = Signal(init=1)
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self.w5500_rst_n = Signal(init=1)
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# Init control
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self.init_req = Signal()
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self.init_done = Signal()
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self.par = Signal(48) # MAC address (PAR0..5 packed)
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# TX stream
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self.tx_data = Signal(8)
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self.tx_valid = Signal()
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self.tx_ready = Signal()
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self.tx_sof = Signal()
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self.tx_eof = Signal()
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# RX stream
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self.rx_data = Signal(8)
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self.rx_valid = Signal()
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self.rx_ready = Signal()
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self.rx_sof = Signal()
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self.rx_eof = Signal()
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def elaborate(self, platform):
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m = Module()
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# ── SPI clock enable ─────────────────────────────────────────────
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# clk_en high every `clk_div` sync cycles. The bit engine toggles SCK
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# on each enabled cycle, so SCK = sync / (2 * clk_div).
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clk_en = Signal()
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if self._clk_div <= 1:
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m.d.comb += clk_en.eq(1) # full rate: SCK = sync/2
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else:
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div_ctr = Signal(range(self._clk_div))
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with m.If(div_ctr == self._clk_div - 1):
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m.d.sync += div_ctr.eq(0)
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with m.Else():
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m.d.sync += div_ctr.eq(div_ctr + 1)
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m.d.comb += clk_en.eq(div_ctr == self._clk_div - 1)
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# ── SPI pin registers (Mode 0: SCK idles LOW) ────────────────────
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sck_r = Signal()
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cs_r = Signal(init=1)
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shift_out = Signal(8)
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shift_in = Signal(8)
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m.d.comb += self.spi_clk .eq(sck_r)
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m.d.comb += self.spi_cs_n.eq(cs_r)
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m.d.comb += self.spi_mosi.eq(shift_out[7]) # MSB first; valid pre-rising
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# ── Byte-transfer engine (Mode 0) ────────────────────────────────
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# On byte_start, shift out byte_tx MSB-first (8 SCK cycles) and capture
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# MISO into byte_rx; pulse byte_done. CS is owned by the xfer engine.
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byte_start = Signal()
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byte_tx = Signal(8)
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byte_rx = Signal(8)
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byte_done = Signal()
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bit_ctr = Signal(4)
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m.d.sync += byte_done.eq(0)
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with m.FSM(domain="sync", name="byte_fsm"):
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with m.State("IDLE"):
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m.d.sync += sck_r.eq(0)
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with m.If(byte_start):
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m.d.sync += shift_out.eq(byte_tx)
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m.d.sync += bit_ctr.eq(0)
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m.next = "RUN"
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with m.State("RUN"):
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with m.If(clk_en):
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with m.If(~sck_r):
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# rising edge: slave samples MOSI, master samples MISO
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m.d.sync += sck_r.eq(1)
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m.d.sync += shift_in.eq(Cat(self.spi_miso, shift_in[:-1]))
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with m.Else():
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# falling edge: advance / finish
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m.d.sync += sck_r.eq(0)
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with m.If(bit_ctr == 7):
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m.d.sync += byte_rx.eq(shift_in)
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m.d.sync += byte_done.eq(1)
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m.next = "IDLE"
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with m.Else():
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m.d.sync += shift_out.eq(Cat(0, shift_out[:-1]))
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m.d.sync += bit_ctr.eq(bit_ctr + 1)
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# ── Generic register transaction engine (Variable Data Mode) ─────
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# One CS-low frame: 3 header bytes (addr_hi, addr_lo, ctrl) then
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# xfer_len payload bytes. Writes source payload from wbuf; reads
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# capture MISO into rbuf.
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WBUF = 8
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xfer_start = Signal()
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xfer_addr = Signal(16)
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xfer_ctrl = Signal(8)
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xfer_len = Signal(range(WBUF + 1))
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xfer_done = Signal()
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wbuf = Array([Signal(8, name=f"wbuf{i}") for i in range(WBUF)])
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rbuf = Array([Signal(8, name=f"rbuf{i}") for i in range(WBUF)])
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xfer_idx = Signal(range(WBUF + 3))
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# Stream-write mode: after the 3-byte header, payload bytes are pulled
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# from (s_data, s_valid, s_last) instead of wbuf, until s_last. Used to
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# forward a frame straight into the W5500 TX buffer. s_consume pulses
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# as each streamed byte is accepted; s_count tracks the byte count.
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xfer_stream = Signal()
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s_data = Signal(8)
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s_valid = Signal()
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s_last = Signal()
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s_consume = Signal()
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s_count = Signal(16)
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s_last_r = Signal() # latched s_last for the in-flight byte
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# Stream-read mode: after the header, read `xfer_rcount` payload bytes
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# (sending 0x00 dummies) and push each out via (r_data, r_valid,
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# r_first, r_last) with r_ready back-pressure. Used to pull a frame
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# out of the W5500 RX buffer into RXFrameAssembler.
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xfer_sread = Signal()
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xfer_rcount = Signal(16)
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r_data = Signal(8)
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r_valid = Signal()
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r_first = Signal()
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r_last = Signal()
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r_ready = Signal()
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r_idx = Signal(16)
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x_byte = Signal(8)
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with m.If(xfer_idx == 0):
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m.d.comb += x_byte.eq(xfer_addr[8:16])
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with m.Elif(xfer_idx == 1):
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m.d.comb += x_byte.eq(xfer_addr[0:8])
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with m.Elif(xfer_idx == 2):
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m.d.comb += x_byte.eq(xfer_ctrl)
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with m.Else():
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m.d.comb += x_byte.eq(wbuf[xfer_idx - 3])
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m.d.comb += byte_start.eq(0)
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m.d.comb += byte_tx.eq(0)
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m.d.comb += s_consume.eq(0)
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m.d.comb += r_valid.eq(0)
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m.d.comb += r_data.eq(0)
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m.d.comb += r_first.eq(0)
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m.d.comb += r_last.eq(0)
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m.d.sync += xfer_done.eq(0)
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with m.FSM(domain="sync", name="xfer_fsm"):
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with m.State("IDLE"):
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with m.If(xfer_start):
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m.d.sync += cs_r.eq(0) # assert CS for the frame
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m.d.sync += xfer_idx.eq(0)
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m.d.sync += s_count.eq(0)
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m.d.sync += r_idx.eq(0)
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m.next = "LOAD"
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with m.State("LOAD"):
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m.d.comb += byte_tx.eq(x_byte)
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m.d.comb += byte_start.eq(1)
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m.next = "WAIT"
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with m.State("WAIT"):
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with m.If(byte_done):
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with m.If(xfer_idx >= 3):
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m.d.sync += rbuf[xfer_idx - 3].eq(byte_rx)
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with m.If((xfer_idx == 2) & xfer_stream):
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m.next = "SLOAD" # stream the payload (write)
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with m.Elif((xfer_idx == 2) & xfer_sread):
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m.next = "RLOAD" # stream the payload (read)
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with m.Elif(~xfer_stream & ~xfer_sread
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& (xfer_idx == (xfer_len + 2))):
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m.next = "FINISH" # 3 header + len − 1
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with m.Else():
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m.d.sync += xfer_idx.eq(xfer_idx + 1)
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m.next = "LOAD"
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# ── Streamed-payload sub-loop (TX buffer write) ──────────────
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with m.State("SLOAD"):
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with m.If(s_valid):
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m.d.comb += byte_tx.eq(s_data)
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m.d.comb += byte_start.eq(1)
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m.d.sync += s_last_r.eq(s_last)
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m.next = "SWAIT"
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with m.State("SWAIT"):
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with m.If(byte_done):
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m.d.comb += s_consume.eq(1) # accept this frame byte
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m.d.sync += s_count.eq(s_count + 1)
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with m.If(s_last_r):
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m.next = "FINISH"
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with m.Else():
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m.next = "SLOAD"
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# ── Streamed-payload sub-loop (RX buffer read) ───────────────
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with m.State("RLOAD"):
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with m.If(r_idx == xfer_rcount):
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m.next = "FINISH"
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with m.Else():
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m.d.comb += byte_tx.eq(0) # dummy MOSI during read
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m.d.comb += byte_start.eq(1)
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m.next = "RWAIT"
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with m.State("RWAIT"):
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with m.If(byte_done):
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m.next = "RPUSH"
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with m.State("RPUSH"):
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m.d.comb += r_data .eq(byte_rx)
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m.d.comb += r_valid.eq(1)
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m.d.comb += r_first.eq(r_idx == 0)
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m.d.comb += r_last .eq(r_idx == (xfer_rcount - 1))
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with m.If(r_ready):
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m.d.sync += r_idx.eq(r_idx + 1)
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m.next = "RLOAD"
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with m.State("FINISH"):
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m.d.sync += cs_r.eq(1) # deassert CS
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m.d.sync += xfer_done.eq(1)
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m.next = "IDLE"
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# Saved MAC for SHAR programming; current W5500 TX write pointer.
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mac_shadow = Array([Signal(8, name=f"mac{i}") for i in range(6)])
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wait_ctr = Signal(range(self._reset_cycles + 2))
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tx_wr = Signal(16)
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rx_rsr = Signal(16) # RX received size
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rx_rd = Signal(16) # RX read pointer
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pkt_len = Signal(16) # MACRAW packet length (incl. 2-byte header)
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# Frame stream from TXFrameDrain feeds the xfer engine's stream port.
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# tx_ready pulses (= s_consume) as each frame byte is taken into the
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# TX-buffer write transaction.
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m.d.comb += [
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s_data .eq(self.tx_data),
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s_valid.eq(self.tx_valid),
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s_last .eq(self.tx_eof),
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self.tx_ready.eq(s_consume),
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]
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# RX buffer read stream → RXFrameAssembler.
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m.d.comb += [
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self.rx_data .eq(r_data),
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self.rx_valid.eq(r_valid),
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self.rx_sof .eq(r_first),
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self.rx_eof .eq(r_last),
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r_ready .eq(self.rx_ready),
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]
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# Helper: a setup state that programs one register-write transaction
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# then waits for it to complete and jumps to `nxt`.
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def write_reg(name, addr, ctrl, payload, nxt):
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with m.State(name):
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m.d.sync += xfer_addr.eq(addr)
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m.d.sync += xfer_ctrl.eq(ctrl)
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m.d.sync += xfer_len.eq(len(payload))
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m.d.sync += xfer_stream.eq(0)
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m.d.sync += xfer_sread.eq(0)
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for i, b in enumerate(payload):
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m.d.sync += wbuf[i].eq(b)
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m.d.sync += xfer_start.eq(1)
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m.next = name + "_W"
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with m.State(name + "_W"):
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m.d.sync += xfer_start.eq(0)
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with m.If(xfer_done):
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m.next = nxt
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# ── Main control FSM ─────────────────────────────────────────────
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with m.FSM(domain="sync", name="main_fsm"):
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with m.State("IDLE"):
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m.d.sync += self.init_done.eq(0)
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with m.If(self.init_req):
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for i in range(6):
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m.d.sync += mac_shadow[i].eq(self.par[i*8:(i+1)*8])
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m.next = "MR_RST"
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with m.Elif(~self.w5500_int_n):
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m.next = "RX_CHECK"
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with m.Elif(self.tx_valid & self.tx_sof):
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m.next = "TX_START"
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# Step 1: MR = 0x80 (software reset), then settle ~1 ms.
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write_reg("MR_RST", _W5500_MR, _CTRL_WR_COMMON, [0x80], "MR_WAIT")
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with m.State("MR_WAIT"):
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with m.If(wait_ctr == self._reset_cycles):
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m.d.sync += wait_ctr.eq(0)
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m.next = "SHAR"
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with m.Else():
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m.d.sync += wait_ctr.eq(wait_ctr + 1)
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# Step 2: SHAR = source MAC (6 bytes from PAR0–5).
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with m.State("SHAR"):
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m.d.sync += xfer_addr.eq(_W5500_SHAR)
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m.d.sync += xfer_ctrl.eq(_CTRL_WR_COMMON)
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m.d.sync += xfer_len.eq(6)
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for i in range(6):
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m.d.sync += wbuf[i].eq(mac_shadow[i])
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m.d.sync += xfer_start.eq(1)
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m.next = "SHAR_W"
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with m.State("SHAR_W"):
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m.d.sync += xfer_start.eq(0)
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with m.If(xfer_done):
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m.next = "S0_MR"
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# Step 3–5: S0_MR=MACRAW, S0_CR=OPEN, S0_IMR=RECV|SEND_OK.
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write_reg("S0_MR", _W5500_S0_MR, _CTRL_WR_S0REG, [0x04], "S0_CR")
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write_reg("S0_CR", _W5500_S0_CR, _CTRL_WR_S0REG, [0x01], "S0_IMR")
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write_reg("S0_IMR", _W5500_S0_IMR, _CTRL_WR_S0REG, [0x05], "INIT_DONE")
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with m.State("INIT_DONE"):
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m.d.sync += self.init_done.eq(1)
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m.next = "IDLE"
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# ── TX path (MACRAW) ─────────────────────────────────────────
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# 1) read S0_TX_WR, 2) stream the frame into the TX buffer at that
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# offset, 3) advance S0_TX_WR by the byte count, 4) issue SEND.
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with m.State("TX_START"):
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m.d.sync += xfer_addr.eq(_W5500_S0_TX_WR)
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m.d.sync += xfer_ctrl.eq(_CTRL_RD_S0REG)
|
||
m.d.sync += xfer_len.eq(2)
|
||
m.d.sync += xfer_stream.eq(0)
|
||
m.d.sync += wbuf[0].eq(0) # read → send 0x00 dummies
|
||
m.d.sync += wbuf[1].eq(0)
|
||
m.d.sync += xfer_start.eq(1)
|
||
m.next = "TX_RDPTR_W"
|
||
with m.State("TX_RDPTR_W"):
|
||
m.d.sync += xfer_start.eq(0)
|
||
with m.If(xfer_done):
|
||
m.d.sync += tx_wr.eq(Cat(rbuf[1], rbuf[0])) # big-endian
|
||
m.next = "TX_DATA"
|
||
|
||
with m.State("TX_DATA"):
|
||
m.d.sync += xfer_addr.eq(tx_wr)
|
||
m.d.sync += xfer_ctrl.eq(_CTRL_WR_S0TX) # socket-0 TX buffer
|
||
m.d.sync += xfer_stream.eq(1)
|
||
m.d.sync += xfer_start.eq(1)
|
||
m.next = "TX_DATA_W"
|
||
with m.State("TX_DATA_W"):
|
||
m.d.sync += xfer_start.eq(0)
|
||
with m.If(xfer_done):
|
||
m.d.sync += xfer_stream.eq(0)
|
||
m.d.sync += tx_wr.eq(tx_wr + s_count) # advanced pointer
|
||
m.next = "TX_UPDPTR"
|
||
|
||
with m.State("TX_UPDPTR"):
|
||
m.d.sync += xfer_addr.eq(_W5500_S0_TX_WR)
|
||
m.d.sync += xfer_ctrl.eq(_CTRL_WR_S0REG)
|
||
m.d.sync += xfer_len.eq(2)
|
||
m.d.sync += xfer_stream.eq(0)
|
||
m.d.sync += wbuf[0].eq(tx_wr[8:16]) # hi (already advanced)
|
||
m.d.sync += wbuf[1].eq(tx_wr[0:8]) # lo
|
||
m.d.sync += xfer_start.eq(1)
|
||
m.next = "TX_UPDPTR_W"
|
||
with m.State("TX_UPDPTR_W"):
|
||
m.d.sync += xfer_start.eq(0)
|
||
with m.If(xfer_done):
|
||
m.next = "TX_SEND"
|
||
|
||
# S0_CR = SEND (0x20)
|
||
write_reg("TX_SEND", _W5500_S0_CR, _CTRL_WR_S0REG, [0x20], "IDLE")
|
||
|
||
# ── RX path (MACRAW) ─────────────────────────────────────────
|
||
# Triggered by W5500 INT (w5500_int_n low): read RX_RSR, read
|
||
# RX_RD, read the 2-byte MACRAW length, stream the frame out,
|
||
# advance RX_RD, issue RECV.
|
||
with m.State("RX_CHECK"): # read S0_RX_RSR
|
||
m.d.sync += xfer_addr.eq(_W5500_S0_RX_RSR)
|
||
m.d.sync += xfer_ctrl.eq(_CTRL_RD_S0REG)
|
||
m.d.sync += xfer_len.eq(2)
|
||
m.d.sync += xfer_stream.eq(0)
|
||
m.d.sync += xfer_sread.eq(0)
|
||
m.d.sync += wbuf[0].eq(0)
|
||
m.d.sync += wbuf[1].eq(0)
|
||
m.d.sync += xfer_start.eq(1)
|
||
m.next = "RX_RSR_W"
|
||
with m.State("RX_RSR_W"):
|
||
m.d.sync += xfer_start.eq(0)
|
||
with m.If(xfer_done):
|
||
m.d.sync += rx_rsr.eq(Cat(rbuf[1], rbuf[0]))
|
||
m.next = "RX_RSR_CHK"
|
||
with m.State("RX_RSR_CHK"):
|
||
with m.If(rx_rsr == 0):
|
||
m.next = "IDLE" # nothing received
|
||
with m.Else():
|
||
m.next = "RX_RDPTR"
|
||
|
||
with m.State("RX_RDPTR"): # read S0_RX_RD
|
||
m.d.sync += xfer_addr.eq(_W5500_S0_RX_RD)
|
||
m.d.sync += xfer_ctrl.eq(_CTRL_RD_S0REG)
|
||
m.d.sync += xfer_len.eq(2)
|
||
m.d.sync += xfer_start.eq(1)
|
||
m.next = "RX_RDPTR_W"
|
||
with m.State("RX_RDPTR_W"):
|
||
m.d.sync += xfer_start.eq(0)
|
||
with m.If(xfer_done):
|
||
m.d.sync += rx_rd.eq(Cat(rbuf[1], rbuf[0]))
|
||
m.next = "RX_LEN"
|
||
|
||
with m.State("RX_LEN"): # read 2-byte MACRAW length
|
||
m.d.sync += xfer_addr.eq(rx_rd)
|
||
m.d.sync += xfer_ctrl.eq(_CTRL_RD_S0RX)
|
||
m.d.sync += xfer_len.eq(2)
|
||
m.d.sync += xfer_start.eq(1)
|
||
m.next = "RX_LEN_W"
|
||
with m.State("RX_LEN_W"):
|
||
m.d.sync += xfer_start.eq(0)
|
||
with m.If(xfer_done):
|
||
m.d.sync += pkt_len.eq(Cat(rbuf[1], rbuf[0]))
|
||
m.next = "RX_FRAME"
|
||
|
||
with m.State("RX_FRAME"): # stream pkt_len−2 frame bytes
|
||
m.d.sync += xfer_addr.eq(rx_rd + 2)
|
||
m.d.sync += xfer_ctrl.eq(_CTRL_RD_S0RX)
|
||
m.d.sync += xfer_sread.eq(1)
|
||
m.d.sync += xfer_rcount.eq(pkt_len - 2)
|
||
m.d.sync += xfer_start.eq(1)
|
||
m.next = "RX_FRAME_W"
|
||
with m.State("RX_FRAME_W"):
|
||
m.d.sync += xfer_start.eq(0)
|
||
with m.If(xfer_done):
|
||
m.d.sync += xfer_sread.eq(0)
|
||
m.next = "RX_UPDRD"
|
||
|
||
with m.State("RX_UPDRD"): # S0_RX_RD += pkt_len
|
||
m.d.sync += xfer_addr.eq(_W5500_S0_RX_RD)
|
||
m.d.sync += xfer_ctrl.eq(_CTRL_WR_S0REG)
|
||
m.d.sync += xfer_len.eq(2)
|
||
m.d.sync += xfer_stream.eq(0)
|
||
m.d.sync += xfer_sread.eq(0)
|
||
m.d.sync += wbuf[0].eq((rx_rd + pkt_len)[8:16])
|
||
m.d.sync += wbuf[1].eq((rx_rd + pkt_len)[0:8])
|
||
m.d.sync += xfer_start.eq(1)
|
||
m.next = "RX_UPDRD_W"
|
||
with m.State("RX_UPDRD_W"):
|
||
m.d.sync += xfer_start.eq(0)
|
||
with m.If(xfer_done):
|
||
m.next = "RX_RECV"
|
||
|
||
# S0_CR = RECV (0x40), then clear the RECV interrupt so INT_N
|
||
# deasserts (write 1 to Sn_IR[2]); otherwise the FSM would re-enter
|
||
# RX_CHECK forever on a real W5500.
|
||
write_reg("RX_RECV", _W5500_S0_CR, _CTRL_WR_S0REG, [0x40], "RX_CLR_IR")
|
||
write_reg("RX_CLR_IR", _W5500_S0_IR, _CTRL_WR_S0REG, [0x04], "IDLE")
|
||
|
||
return m
|
||
|
||
|
||
# ── Testbench ─────────────────────────────────────────────────────────────
|
||
|
||
if __name__ == "__main__":
|
||
import sys
|
||
from amaranth.sim import Simulator, Period
|
||
|
||
# Short reset wait so the init sequence runs quickly in simulation.
|
||
dut = W5500SPIMaster(reset_cycles=10)
|
||
errors = []
|
||
|
||
# MAC for SHAR: par[i*8:(i+1)*8] = mac byte i → mac = 11 22 33 44 55 66
|
||
MAC = [0x11, 0x22, 0x33, 0x44, 0x55, 0x66]
|
||
PAR = sum(b << (8 * i) for i, b in enumerate(MAC))
|
||
|
||
# Expected W5500 init transactions: [addr_hi, addr_lo, ctrl, *payload].
|
||
# ctrl 0x04 = common-block write (VDM); 0x0C = socket-0-reg write (VDM).
|
||
EXPECTED = [
|
||
[0x00, 0x00, 0x04, 0x80], # MR = 0x80 (reset)
|
||
[0x00, 0x09, 0x04, *MAC], # SHAR = MAC
|
||
[0x00, 0x00, 0x0C, 0x04], # S0_MR = MACRAW
|
||
[0x00, 0x01, 0x0C, 0x01], # S0_CR = OPEN
|
||
[0x00, 0x2C, 0x0C, 0x05], # S0_IMR = RECV|SEND_OK
|
||
]
|
||
|
||
txns = [] # transactions captured by the W5500 slave model
|
||
|
||
# RX frame the W5500 will hand back, and the MACRAW length it reports.
|
||
RX_FRAME = [0xDE, 0xAD, 0xBE, 0xEF, 0x01, 0x02]
|
||
RX_PKT_LEN = len(RX_FRAME) + 2 # MACRAW length includes the header
|
||
|
||
def build_response(bsb, addr):
|
||
"""Bytes the W5500 drives on MISO for a read of (bsb, addr)."""
|
||
if bsb == 1 and addr == _W5500_S0_RX_RSR:
|
||
return [(RX_PKT_LEN >> 8) & 0xFF, RX_PKT_LEN & 0xFF]
|
||
if bsb == 1 and addr == _W5500_S0_RX_RD:
|
||
return [0x00, 0x00] # RX read pointer = 0
|
||
if bsb == 3 and addr == 0x0000:
|
||
return [(RX_PKT_LEN >> 8) & 0xFF, RX_PKT_LEN & 0xFF] # length
|
||
if bsb == 3 and addr == 0x0002:
|
||
return list(RX_FRAME) # frame payload
|
||
return [0x00] * 64
|
||
|
||
async def w5500_model(ctx):
|
||
"""W5500 SPI slave model: captures CS-framed transactions (MOSI) and,
|
||
for reads, drives MISO with canned register/buffer data. Mode 0:
|
||
MOSI sampled on rising SCK, MISO shifted out MSB-first.
|
||
"""
|
||
prev_cs, prev_sck = 1, 0
|
||
rx_byte = rx_bits = nbytes = 0
|
||
hdr = [0, 0, 0]
|
||
is_read = False
|
||
resp, ridx = [], 0
|
||
msr = msr_bits = 0
|
||
cur_txn = []
|
||
async for vals in ctx.tick("sync").sample(
|
||
dut.spi_cs_n, dut.spi_clk, dut.spi_mosi):
|
||
cs, sck, mosi = vals[-3:]
|
||
rising = (prev_sck == 0 and sck == 1)
|
||
|
||
if prev_cs == 1 and cs == 0: # CS falling: start frame
|
||
cur_txn = []
|
||
rx_byte = rx_bits = nbytes = 0
|
||
is_read = False
|
||
resp, ridx, msr, msr_bits = [], 0, 0, 0
|
||
|
||
if cs == 0 and rising:
|
||
# MISO bit just sampled by the master → advance shift register
|
||
if is_read and nbytes >= 3:
|
||
msr = (msr << 1) & 0xFF
|
||
msr_bits -= 1
|
||
if msr_bits == 0:
|
||
msr = resp[ridx] if ridx < len(resp) else 0
|
||
ridx += 1
|
||
msr_bits = 8
|
||
# sample MOSI
|
||
rx_byte = ((rx_byte << 1) | mosi) & 0xFF
|
||
rx_bits += 1
|
||
if rx_bits == 8:
|
||
cur_txn.append(rx_byte)
|
||
if nbytes < 3:
|
||
hdr[nbytes] = rx_byte
|
||
if nbytes == 2: # header complete → decode
|
||
ctrl = hdr[2]
|
||
is_read = (ctrl & 0x04) == 0
|
||
bsb = ctrl >> 3
|
||
addr = (hdr[0] << 8) | hdr[1]
|
||
if is_read:
|
||
resp = build_response(bsb, addr)
|
||
msr, ridx, msr_bits = resp[0], 1, 8
|
||
nbytes += 1
|
||
rx_byte = rx_bits = 0
|
||
|
||
if prev_cs == 0 and cs == 1: # CS rising: end frame
|
||
txns.append(list(cur_txn))
|
||
|
||
ctx.set(dut.spi_miso, (msr >> 7) & 1)
|
||
prev_cs, prev_sck = cs, sck
|
||
|
||
rx_collected = []
|
||
|
||
async def rx_collector(ctx):
|
||
async for vals in ctx.tick("sync").sample(
|
||
dut.rx_valid, dut.rx_ready, dut.rx_data):
|
||
valid, ready, data = vals[-3:]
|
||
if valid and ready:
|
||
rx_collected.append(data)
|
||
|
||
async def testbench(ctx):
|
||
ctx.set(dut.par, PAR)
|
||
await ctx.tick("sync").repeat(4)
|
||
|
||
# T1: SPI idle — CLK low (Mode 0), CS high
|
||
if ctx.get(dut.spi_clk) != 0:
|
||
errors.append("T1 CLK idle != 0")
|
||
if ctx.get(dut.spi_cs_n) != 1:
|
||
errors.append("T1 CS idle != 1")
|
||
print(f"T1 idle: CLK={ctx.get(dut.spi_clk)} CS={ctx.get(dut.spi_cs_n)}")
|
||
|
||
# T2: run the init sequence
|
||
ctx.set(dut.init_req, 1)
|
||
await ctx.tick("sync").repeat(1)
|
||
ctx.set(dut.init_req, 0)
|
||
|
||
for _ in range(4000):
|
||
await ctx.tick("sync").repeat(1)
|
||
if ctx.get(dut.init_done):
|
||
break
|
||
if not ctx.get(dut.init_done):
|
||
errors.append("T2 init_done never asserted")
|
||
await ctx.tick("sync").repeat(4)
|
||
print(f"T2 init_done: {ctx.get(dut.init_done)}")
|
||
|
||
# T3: verify the captured init transaction sequence
|
||
print(f"T3 captured {len(txns)} init transactions:")
|
||
for t in txns:
|
||
print(" ", [f"0x{b:02X}" for b in t])
|
||
if txns != EXPECTED:
|
||
errors.append(f"T3 init sequence mismatch:\n got {txns}\n want {EXPECTED}")
|
||
|
||
# ── T4: TX a frame (MACRAW) ──────────────────────────────────────
|
||
txns.clear()
|
||
FRAME = [0xAA, 0xBB, 0xCC, 0xDD]
|
||
# With MISO=0 the read returns S0_TX_WR = 0x0000.
|
||
TX_EXPECTED = [
|
||
[0x00, 0x24, 0x08, 0x00, 0x00], # read S0_TX_WR (dummies)
|
||
[0x00, 0x00, 0x14, *FRAME], # write TX buffer @ 0x0000
|
||
[0x00, 0x24, 0x0C, 0x00, len(FRAME)], # S0_TX_WR += len
|
||
[0x00, 0x01, 0x0C, 0x20], # S0_CR = SEND
|
||
]
|
||
|
||
async def send_frame(frame):
|
||
for i, b in enumerate(frame):
|
||
ctx.set(dut.tx_data, b)
|
||
ctx.set(dut.tx_valid, 1)
|
||
ctx.set(dut.tx_sof, 1 if i == 0 else 0)
|
||
ctx.set(dut.tx_eof, 1 if i == len(frame) - 1 else 0)
|
||
for _ in range(2000):
|
||
if ctx.get(dut.tx_ready):
|
||
break
|
||
await ctx.tick("sync").repeat(1)
|
||
await ctx.tick("sync").repeat(1) # complete the consume
|
||
ctx.set(dut.tx_valid, 0)
|
||
ctx.set(dut.tx_sof, 0)
|
||
ctx.set(dut.tx_eof, 0)
|
||
|
||
await send_frame(FRAME)
|
||
# let the pointer-update + SEND transactions finish
|
||
for _ in range(2000):
|
||
await ctx.tick("sync").repeat(1)
|
||
if len(txns) >= len(TX_EXPECTED):
|
||
break
|
||
await ctx.tick("sync").repeat(4)
|
||
|
||
print(f"T4 captured {len(txns)} TX transactions:")
|
||
for t in txns:
|
||
print(" ", [f"0x{b:02X}" for b in t])
|
||
if txns != TX_EXPECTED:
|
||
errors.append(f"T4 TX sequence mismatch:\n got {txns}\n want {TX_EXPECTED}")
|
||
|
||
# ── T5: RX a frame (MACRAW) ──────────────────────────────────────
|
||
# The model returns RSR=pkt_len, RD=0, MACRAW length=pkt_len, then the
|
||
# frame. Expected transactions (read dummies are 0x00):
|
||
RX_EXPECTED = [
|
||
[0x00, 0x26, 0x08, 0x00, 0x00], # read S0_RX_RSR
|
||
[0x00, 0x28, 0x08, 0x00, 0x00], # read S0_RX_RD
|
||
[0x00, 0x00, 0x18, 0x00, 0x00], # read MACRAW length
|
||
[0x00, 0x02, 0x18, *([0x00] * len(RX_FRAME))], # read frame
|
||
[0x00, 0x28, 0x0C, 0x00, RX_PKT_LEN], # S0_RX_RD += pkt_len
|
||
[0x00, 0x01, 0x0C, 0x40], # S0_CR = RECV
|
||
[0x00, 0x02, 0x0C, 0x04], # S0_IR clear RECV
|
||
]
|
||
txns.clear()
|
||
ctx.set(dut.rx_ready, 1)
|
||
ctx.set(dut.w5500_int_n, 0) # signal a received packet
|
||
for _ in range(4000):
|
||
await ctx.tick("sync").repeat(1)
|
||
if len(txns) >= len(RX_EXPECTED):
|
||
break
|
||
ctx.set(dut.w5500_int_n, 1)
|
||
await ctx.tick("sync").repeat(8)
|
||
|
||
print(f"T5 captured {len(txns)} RX transactions:")
|
||
for t in txns:
|
||
print(" ", [f"0x{b:02X}" for b in t])
|
||
print(f"T5 rx frame: {[f'0x{b:02X}' for b in rx_collected]} "
|
||
f"(want {[f'0x{b:02X}' for b in RX_FRAME]})")
|
||
if txns != RX_EXPECTED:
|
||
errors.append(f"T5 RX sequence mismatch:\n got {txns}\n want {RX_EXPECTED}")
|
||
if rx_collected != RX_FRAME:
|
||
errors.append(f"T5 RX frame mismatch: got {rx_collected}, want {RX_FRAME}")
|
||
|
||
sim = Simulator(dut)
|
||
sim.add_clock(Period(MHz=24), domain="sync")
|
||
sim.add_testbench(testbench)
|
||
sim.add_process(w5500_model)
|
||
sim.add_process(rx_collector)
|
||
|
||
with sim.write_vcd("W5500SPIMaster.vcd"):
|
||
sim.run()
|
||
|
||
if errors:
|
||
print("\nFAILURES:")
|
||
for e in errors:
|
||
print(" ", e)
|
||
sys.exit(1)
|
||
else:
|
||
print("\nAll tests passed.")
|