Roflin a5e1adbff3 TODO: resolve D4/D5 question - keep USBLC6 flow-through as designed ...

Record the verdict so it isn't relitigated: USBLC6 is ST-rated for
Ethernet, PHY-side placement is standard practice, floating VBUS is
deliberate (3.3V-biased lines would clip against a tied rail), and the
split PHY_*/ETH_* nets force zero-stub flow-through routing - the
better ESD topology. Earlier stub/DNP suggestion withdrawn.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

2026-07-18 13:07:01 +00:00

..

re-bba-rb

TODO: resolve D4/D5 question - keep USBLC6 flow-through as designed

2026-07-18 13:07:01 +00:00

sp1_test_plug

Started on component selection of the final PCB.

2026-06-13 22:09:05 +02:00

.gitignore

Start of a new debug connector

2025-09-19 12:06:05 +02:00

HANRUN_HR911105A.kicad_mod

Played around with board shape/layout Changed USB power tree

2026-06-26 22:07:59 +02:00

HANRUN_HR961160C.kicad_mod

Played around with board shape/layout Changed USB power tree

2026-06-26 22:07:59 +02:00

HR911105A.kicad_sym

finalized pcb design, need to remeasure PCB outline.

2026-07-08 22:00:53 +02:00

HR961160C.kicad_sym

Played around with board shape/layout Changed USB power tree

2026-06-26 22:07:59 +02:00

J1B1211CCD.kicad_mod

Started on component selection of the final PCB.

2026-06-13 22:09:05 +02:00

J1B1211CCD.kicad_sym

Started on component selection of the final PCB.

2026-06-13 22:09:05 +02:00

PUSB3AB6Z_ES.kicad_sym

Finished the PCB design

2026-07-17 21:35:02 +02:00

SON50P110X213X50-7.kicad_mod

Finished the PCB design

2026-07-17 21:35:02 +02:00

SOT95P280X110-6N.kicad_mod

Started on a 4 layer board with cutout for interposer

2026-06-27 22:25:03 +02:00

SP1 BoardConnector.kicad_mod

finalized pcb design, need to remeasure PCB outline.

2026-07-08 22:00:53 +02:00

TPS562201DDCR.kicad_sym

finalized pcb design, need to remeasure PCB outline.

2026-07-08 22:00:53 +02:00

USB_C_Receptacle_Hanbo-MC-711-H72.kicad_mod

Fixes the power traces.

2026-07-09 20:08:05 +02:00