Dennis Brentjes
108 lines
3.2 KiB
Python
108 lines
3.2 KiB
Python
from amaranth import *
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from amaranth.sim import Simulator
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class SyncFF(Elaboratable):
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"""Width-N multi-flop synchronizer from `src_domain` to `dst_domain`.
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Use when the source is a level signal that may be stable for multiple destination
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cycles. Not suitable for single-cycle pulses (use TogglePulseSync instead).
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"""
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def __init__(self, width=1, src_domain="src", dst_domain="dst"):
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self.width = width
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self.src_domain = src_domain
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self.dst_domain = dst_domain
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self.src = Signal(self.width)
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self.dst = Signal(self.width)
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def elaborate(self, platform):
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m = Module()
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reg_src = Signal(self.width)
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ff0 = Signal(self.width)
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ff1 = Signal(self.width)
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m.d[self.src_domain] += reg_src.eq(self.src)
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m.d[self.dst_domain] += ff0.eq(reg_src)
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m.d[self.dst_domain] += ff1.eq(ff0)
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m.d.comb += self.dst.eq(ff1)
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return m
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class TogglePulseSync(Elaboratable):
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"""Reliable pulse transfer from `src_domain` into `dst_domain`.
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- Source toggles `toggle` whenever an event occurs.
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- Destination synchronizes the toggle and detects edges.
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Guarantees ordering and no lost pulses for single-bit events.
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"""
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def __init__(self, src_domain="src", dst_domain="dst"):
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self.src_domain = src_domain
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self.dst_domain = dst_domain
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self.src_pulse = Signal()
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self.dst_pulse = Signal()
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def elaborate(self, platform):
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m = Module()
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toggle = Signal()
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sync0 = Signal()
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sync1 = Signal()
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prev = Signal()
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edge = Signal()
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# Source domain: flip the toggle when a pulse arrives
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m.d[self.src_domain] += If(self.src_pulse, toggle.eq(~toggle))
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# Destination domain: two-flop synchronize the toggle
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m.d[self.dst_domain] += sync0.eq(toggle)
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m.d[self.dst_domain] += sync1.eq(sync0)
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# Detect the change in the destination domain
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m.d[self.dst_domain] += edge.eq(sync1 ^ prev)
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m.d[self.dst_domain] += prev.eq(sync1)
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m.d.comb += self.dst_pulse.eq(edge)
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return m
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def _sim_toggle_pulse():
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"""Simple simulation that drives pulses on the source domain and prints detections on the destination domain."""
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top = Module()
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t = TogglePulseSync(src_domain="src", dst_domain="dst")
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top.submodules.t = t
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sim = Simulator(top)
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# Create two asynchronous clocks (periods chosen arbitrarily for the sim)
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sim.add_clock(1e-6, domain="src")
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sim.add_clock(1.5e-6, domain="dst")
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def process():
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# Wait a little, then generate three source pulses at different phases
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for _ in range(5):
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yield
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for i in range(3):
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yield t.src_pulse.eq(1)
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yield
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yield t.src_pulse.eq(0)
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# let the domains run for a few cycles
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for _ in range(10):
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dp = (yield t.dst_pulse)
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if dp:
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print(f"dst detected pulse at sim tick")
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yield
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# run a bit longer to observe behavior
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for _ in range(20):
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yield
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sim.add_sync_process(process, domain="src")
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sim.run_until(100e-6)
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if __name__ == "__main__":
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_sim_toggle_pulse()
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