RoflinandClaude Opus 5 5f60c011cb fix(w5100): clear stale Sn_IR bits when INT_N asserts with no RX data ...

RX_RSR_CHK returned to IDLE when RSR==0 without clearing Sn_IR.  SEND_OK
(bit 4) fires after every successful transmit and the RX path only ever
cleared RECV (bit 2), so INT_N stayed asserted; because IDLE tests
~w5100_int_n BEFORE tx_valid, the FSM span IDLE->RX_CHECK->RX_RSR_CHK->IDLE
and TX was starved permanently.  Observed on hardware as the first frame
transmitting and every later one never setting TI while RX kept working.

Now clears every Sn_IR bit except RECV, so a frame arriving between the RSR
read and the write still raises INT_N and is served next pass.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

2026-09-30 19:16:51 +00:00

..

__init__.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

bba_register_file.py

fix(tx): queue the frame length at TWD_HI so the drain runs concurrently

2026-09-30 18:49:04 +00:00

bba_top.py

fix(w5100): wait 83ms after software reset, not 1ms

2026-09-30 19:02:52 +00:00

diagram.py

Adds diagrams.

2026-06-13 19:02:58 +02:00

eeprom_model.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

exi_capture.py

Add integrated UART UDP bring-up shell (socket 3) + capture critical-path fix

2026-08-02 14:36:47 +00:00

exi_j4.py

exi_j4: shared AND-merge helper + enumeration testbench

2026-09-30 18:12:26 +00:00

rx_frame_assembler.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

spi_mode3_slave.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

spram_arbiter.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

status_panel.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00

synth.py

synth: optional EXI mirror on the J4 debug header (EXI_J4=1)

2026-09-30 17:54:24 +00:00

tx_frame_drain.py

fix(tx): queue the frame length at TWD_HI so the drain runs concurrently

2026-09-30 18:49:04 +00:00

uart_console.py

Added Uart.

2026-06-14 09:37:59 +02:00

uart_shell.py

Add integrated UART UDP bring-up shell (socket 3) + capture critical-path fix

2026-08-02 14:36:47 +00:00

w5100_parallel_master.py

fix(w5100): clear stale Sn_IR bits when INT_N asserts with no RX data

2026-09-30 19:16:51 +00:00

w5100_regdump.py

Add W5100 read-only register-dump probe (bring-up)

2026-09-20 15:03:44 +00:00

w5100_selftest.py

fix(w5100): unlock NETLCKR before writing GWR/SUBR/SHAR/SIPR (W5100S)

2026-09-20 14:51:33 +00:00

w5100_udptest.py

Hardware bring-up: first UDP packet transmitted and captured

2026-09-20 19:10:07 +00:00

w5500_spi_master.py

Added full design created with Claude

2026-06-13 18:35:38 +02:00