Completes the WIZnet reference schematic for the MDI section:
- R32-R35 3.3R 1% (YAGEO RC0402FR-073R3L, LCSC C137986) in series in
each MDI line per WIZnet note 6 (EMI damping). Chain per line is now
U11 pin -> 49.9R termination tap -> 3.3R -> D4/D5 flow-through -> J2.
Chip-side nets keep PHY_*; the D4/D5-side segments are renamed MDI_*
and added to the ETH_DP netclass patterns so the impedance DRC rules
police both halves.
- C20 100nF (C1525) + C21 1uF (C15849) on ETH_3V3 per WIZnet note 7 -
to be placed AT J2 pins 4/5 tapping the In2 ETH_3V3 island.
(Also carries KiCad's resave/reposition of ethernet.kicad_sch from the
rework session - netlist-identical, verified.)
Verified: ERC 0, netlist 121 components vs BOM 120 (J3-only delta),
PHY_TX_P = {U11.3, R26.1, R32.1}, MDI_TX_P = {R32.2, D4.1}, and
likewise for all four lines. PCB: 6 footprints to place (cut the lines
between termination and D4/D5 for R32-R35; C20/C21 at the jack).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Roflin
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