An audit for signals that are written but never read, ports nothing wires, and
constants only the tests touch turned up something bigger than stray signals:
the whole rx_rptr SyncFIFO was dead.
asm.rrp is wired from reg.rrp -- the combinational tap -- and the FIFO's far
side (rx_rptr_r_data / _r_en / _r_rdy) is wired NOWHERE in BBATop. It is a
leftover from when the register file and the frame assembler sat in different
clock domains; when those merged the direct tap replaced it and the FIFO was
never removed. Gone: a 4x8 SyncFIFO, its write logic in the RRP case, its
default strobe and three ports.
Also removed _RWP_HI and _RRP_HI, which were never referenced. The register
table now says why instead: the ring is 15 pages, so the high bytes of both
pointers are always zero and the read mux's default already returns that.
NCRB_PR went the other way -- it was used only by a test while BBATop steered
the ethernet address filter from a bare `reg.ncrb[0]`. It is now public and
BBATop imports it, so the constant is live and the magic index is gone.
Kept deliberately: _NCRB_PM and _NCRB_AB are referenced only by T15, but they
document the filtering bits of a real register and make that assertion
readable, so they stay.
Area went DOWN, which is the evidence the FIFO was real logic rather than
something yosys had already pruned:
ICESTORM_LC 4350 original -> 4380 after the docs pass -> 4328 now
Full suite passes, bba_top passes at EXI_HALF=1/2/8.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Roflin
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