Roflin
abc61f3e66
First on-console run: the Identity suite failed with the device ID reading 00 00 00 10 instead of 04 02 02 00. Bit analysis shows that is an EXACT match for the correct stream delayed by 22 bits -- the device answers correctly, just too late for a 32-clock window to catch more than its first set bit. Not corruption, and not a broken link: response latency. At EXI index 5 (~27 MHz) 22 bit-times is ~815 ns, which is about what the CDC chain costs (rx AsyncFIFO capture->exi, register-file decode, tx AsyncFIFO exi->capture, SPI engine) at a 24 MHz exi clock. The design expects the GC to hold the clock idle between the header write and the data read so the register file can prefetch the response; libogc's inter-call overhead alone is not enough at full speed. Adds bba_gap_us (default 16 us, busy-waited with CS asserted since we hold the EXI lock) and a Gap sweep test that reports the minimum clean gap at the current speed -- which measures the latency rather than guessing at it. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
85 lines
3.0 KiB
C
85 lines
3.0 KiB
C
/* bba.h — raw EXI transport to the re-bba-rb adapter in Serial Port 1.
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*
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* Deliberately NOT libogc's bba network driver: this talks to the register
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* file directly so every check gets its own pass/fail and a failure points at
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* a specific register rather than at "networking".
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*/
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#ifndef BBA_H
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#define BBA_H
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#include <gccore.h>
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/* Serial Port 1 == EXI channel 0, device 2. */
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#define BBA_EXI_CHAN EXI_CHANNEL_0
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#define BBA_EXI_DEV EXI_DEVICE_2
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/* Register map (see CLAUDE.md "Key Registers"). */
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#define REG_NCRA 0x00
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#define REG_IMR 0x08
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#define REG_IR 0x09
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#define REG_RWP_LO 0x16
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#define REG_RWP_HI 0x17
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#define REG_RRP_LO 0x18
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#define REG_PAR0 0x20
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#define REG_PAR4 0x24
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#define REG_NWAYS 0x31
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#define REG_TWD_LO 0x34
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#define REG_TWD_HI 0x35
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#define REG_HIPR 0x3A
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#define REG_TXDATA 0x48
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#define SPRAM_BASE 0x0100
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/* NCRA bits */
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#define NCRA_RESET 0x01
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#define NCRA_ST0 0x02
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#define NCRA_SR 0x08
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/* IR bits */
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#define IR_RI 0x02
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#define IR_TI 0x04
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/* Expected constants */
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#define NWAYS_LINKUP 0x17
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#define HIPR_PRESENT 0x01
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/* EXI clock index, EXI_SPEED1MHZ(0) .. EXI_SPEED32MHZ(5). The nominal 32 MHz
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* index is really ~27 MHz on hardware (see CLAUDE.md); the capture domain
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* oversamples it 2x at 54 MHz. Settable so the suite can sweep it. */
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extern u32 bba_speed;
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/* Microseconds to hold the clock idle between the header write and the data
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* phase, with CS still asserted. The register file decodes the header and
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* PROACTIVELY pushes the response into its TX FIFO during this gap; until the
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* first byte reaches the FIFO head the device drives MISO low. Measured on
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* hardware 2026-10-03: at EXI index 5 the reply arrived 22 bit-times (~815 ns)
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* late with no explicit gap, so a 4-byte read returned 00 00 00 10 -- the
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* correct stream, just shifted out of the window. 0 = whatever gap libogc's
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* inter-call overhead happens to give. */
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extern u32 bba_gap_us;
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/* All return 0 on success, negative on an EXI-layer failure. */
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/* Immediate read of `len` (1..4) bytes from `addr`.
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* Clocks EXACTLY `len` bytes: over-clocking a register read leaves stale
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* prefetched bytes queued in the gateware and desynchronises the NEXT
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* transaction (hardware-confirmed 2026-09-30). Never pad this. */
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int bba_read(u16 addr, void *buf, u32 len);
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/* Immediate write of `len` (1..4) bytes to `addr`. */
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int bba_write(u16 addr, const void *buf, u32 len);
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/* Convenience single-byte helpers. bba_r8 returns the byte, or <0 on error. */
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int bba_r8(u16 addr);
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int bba_w8(u16 addr, u8 val);
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/* SPRAM / DMA-style read: any address >= 0x0100 streams until CS deasserts,
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* so `len` may exceed 4 and the header's 2-bit length field is ignored. */
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int bba_stream(u16 addr, void *buf, u32 len);
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/* Stream `len` bytes into the TXDATA port. One byte per EXI transaction:
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* the register file's effective address auto-increments per data byte, so a
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* multi-byte write to 0x48 would spill into 0x49+ instead of the FIFO. */
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int bba_tx_bytes(const u8 *buf, u32 len);
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#endif
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