40 lines
974 B
Systemverilog
40 lines
974 B
Systemverilog
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`ifndef SVA_COMMON_SVH
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`define SVA_COMMON_SVH
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`ifdef SVA_ENABLE
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`define SVA_DEF_CLK(clk) \
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logic sva_clk; \
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assign sva_clk = clk;
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`define SVA_DEF_NRESET(nrst) \
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logic sva_nreset; \
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assign sva_nreset = nrst;
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`define SVA_ASSERT_PROP(label, prop, err) \
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property label``_prop; \
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@(posedge sva_clk) disable iff (!nreset) \
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(prop); \
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endproperty \
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label``_sva: assert property (label``_prop) else $display($sformatf("[%0t] %s", $time, err));
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`define SVA_ASSERT_PROP_FATAL(label, prop, err) \
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property label``_prop; \
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@(posedge sva_clk) disable iff (!nreset) \
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(prop); \
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endproperty \
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label``_sva: assert property (label``_prop) else begin \
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$display($sformatf("[%0t] %s", $time, err)); \
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$fatal(); \
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end
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`else /* SVA_ENABLE */
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`define SVA_DEF_CLK(clk)
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`define SVA_DEF_NRESET(nrst)
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`define SVA_ASSERT_PROP(label, prop, err)
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`define SVA_ASSERT_PROP_FATAL(label, prop, err)
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`endif /* SVA_ENABLE */
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`endif /* SVA_COMMON_SVH */
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