32 lines
497 B
Systemverilog
32 lines
497 B
Systemverilog
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`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module cpu (
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input logic clk_i,
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input logic nreset_i,
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output logic [15:0] address_o,
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input logic [ 7:0] rdata_i
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);
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state_t state;
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logic [15:0] pc;
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control control_inst (
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.clk_i (clk_i),
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.nreset_i(nreset_i),
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.state_o (state),
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.pc_o (pc)
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);
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registers registers_inst (
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.clk_i (clk_i),
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.nreset_i(nreset_i)
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);
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assign address_o = pc;
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endmodule : cpu
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