svgb/rtl/cart.sv

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module cart (
input wire clk,
input wire nreset,
input wire nrd_i,
input wire nwr_i,
input wire ncs_i,
input wire [15:0] addr_i,
inout wire [ 7:0] data_io
);
logic cs;
logic [ 7:0] rom_rdata;
assign cs = ~ncs_i;
assign data_io = (cs & ~nrd_i) ? rom_rdata : 'Z;
rom #(
.FILE_NAME("tetris.gb"),
.ADDR_W (14),
.DATA_W (8)
) rom_inst (
.clk (clk),
.nreset (nreset),
.cs_i (cs),
.address_i(addr_i[13:0]),
.rdata_o (rom_rdata)
);
endmodule : cart