svgb/sim/clkgen.sv

module clkgen #(
PERIOD_NS      = 10,
RESET_DELAY_NS = 45
) (
  output logic clk,
  output logic nreset
);

initial begin
  clk    = 1'b1;
  nreset = 1'b0;
  #RESET_DELAY_NS nreset = 1'b1;
end

always
  #(PERIOD_NS/2) clk <= ~clk;

endmodule
Complete rewrite from scratch, bootstrap WIP Rewrite to use several bus multiplexers, resulting into a less messy microarchitecture (hopefully). Some more room for cleanup though... Supports every instruction from the bootstrap rom, more or less. LY hacked at 0x90 to progress through vsync instantly. No cartridge is present yet, so we will always fail checksum test and lock up. 2023-10-02 00:00:56 +02:00			`module clkgen #(`
			`PERIOD_NS = 10,`
			`RESET_DELAY_NS = 45`
			`) (`
			`output logic clk,`
			`output logic nreset`
			`);`

			`initial begin`
Fix some verilog issues 2023-10-03 23:30:36 +02:00			`clk = 1'b1;`
			`nreset = 1'b0;`
			`#RESET_DELAY_NS nreset = 1'b1;`
Complete rewrite from scratch, bootstrap WIP Rewrite to use several bus multiplexers, resulting into a less messy microarchitecture (hopefully). Some more room for cleanup though... Supports every instruction from the bootstrap rom, more or less. LY hacked at 0x90 to progress through vsync instantly. No cartridge is present yet, so we will always fail checksum test and lock up. 2023-10-02 00:00:56 +02:00			`end`

			`always`
			`#(PERIOD_NS/2) clk <= ~clk;`

			`endmodule`