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`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module decode (
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input logic [7:0] instr0_i,
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input logic [7:0] instr1_i,
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input logic [7:0] instr2_i,
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input state_t state_i,
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output logic need_instr1_o,
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output logic need_instr2_o,
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output logic undef_o,
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output logic sp_we_o,
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output sp_src_t sp_src_o,
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output logic alu_op_valid_o,
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output alu_op_t alu_op_o,
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output op_src_t op_src_o,
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output op_dest_t op_dest_o,
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output alu16_op_t alu16_op_o,
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output reg16_t reg16_dest_o,
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output reg16_t reg16_src_o,
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output adr_src_t adr_src_o,
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output logic memory_we_o
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);
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logic [1:0] dec_x;
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logic [2:0] dec_y;
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logic [2:0] dec_z;
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logic [1:0] dec_p;
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logic dec_q;
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logic is_ld_rr_nnnn;
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logic is_ld_sp_nnnn;
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logic is_ldd_hl_a;
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logic is_alu_a_n;
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assign dec_x = instr0_i[7:6];
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assign dec_y = instr0_i[5:3];
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assign dec_z = instr0_i[2:0];
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assign dec_p = instr0_i[5:4];
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assign dec_q = instr0_i[3];
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assign is_ld_rr_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p != 2'h3);
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assign is_ld_sp_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p == 2'h3);
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assign is_ldd_hl_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h3);
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assign is_alu_a_n = (dec_x == 3'h2);
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assign need_instr1_o = is_ld_sp_nnnn | is_ld_rr_nnnn;
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assign need_instr2_o = is_ld_sp_nnnn | is_ld_rr_nnnn;
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assign undef_o = ~(is_ld_sp_nnnn | is_ld_rr_nnnn | is_alu_a_n | is_ldd_hl_a);
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assign sp_we_o = is_ld_sp_nnnn & (state_i == ST4_EXEC);
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assign alu_op_valid_o = is_alu_a_n;
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assign alu_op_o = alu_op_t'(dec_y);
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assign op_dest_o = is_alu_a_n ? OP_DEST_A :
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is_ld_rr_nnnn ? OP_DEST_REG16 :
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is_ldd_hl_a ? OP_DEST_REG16 :
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op_dest_t'('X);
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assign op_src_o = is_alu_a_n ? OP_SRC_REG8 :
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is_ld_rr_nnnn ? OP_SRC_OPERAND16 :
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is_ldd_hl_a ? OP_SRC_REG16 :
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op_src_t'('X);
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assign reg16_src_o = is_ldd_hl_a ? REG16_HL : reg16_t'(dec_p);
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assign reg16_dest_o = is_ldi_hl_a ? REG16_HL : reg16_t'(dec_p);
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assign adr_src_o = is_ldi_hl_a ? ADR_SRC_HL :
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ADR_SRC_PC;
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assign memory_we_o = is_ldi_hl_a;
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endmodule : decode
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