svgb/build/tb_top.Makefile

TB       = tb_top
SOURCES  = gb.sv cpu.sv alu.sv registers.sv control.sv decode.sv rom.sv ram.sv tb_top.sv clkgen.sv
INCLUDES = cpu_pkg.svh
PATH_SRC = ../rtl:../rtl/cpu:../rtl/shared:../sim/tbench:../sim/shared

include ../synthflow/vivado/Makefile.rules
Initial work on build system Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module. 2021-02-15 22:40:12 +01:00			`TB = tb_top`
Implement RLA and POP RR 2022-02-09 00:53:02 +01:00			`SOURCES = gb.sv cpu.sv alu.sv registers.sv control.sv decode.sv rom.sv ram.sv tb_top.sv clkgen.sv`
Update synthflow and adapt makefile 2022-02-08 17:14:13 +01:00			`INCLUDES = cpu_pkg.svh`
Initial work on reading instructions from bootROM 2021-02-15 23:55:09 +01:00			`PATH_SRC = ../rtl:../rtl/cpu:../rtl/shared:../sim/tbench:../sim/shared`

Update synthflow and adapt makefile 2022-02-08 17:14:13 +01:00			`include ../synthflow/vivado/Makefile.rules`
Initial work on build system Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module. 2021-02-15 22:40:12 +01:00