From 06746f71fb9bc05405ec44c43c47f49958e5e0bd Mon Sep 17 00:00:00 2001
From: Koray Yanik <fumyuun@gmail.com>
Date: Tue, 3 Oct 2023 20:44:28 +0100
Subject: [PATCH] WIP PPU LX/LY registers

Removed second reg16 read port - no longer needed.
---
 build/tb_top.Makefile |  2 +-
 rtl/cpu/regbank.sv    |  3 ---
 rtl/{ => ppu}/ppu.sv  | 25 +++++++++++++++++++++----
 3 files changed, 22 insertions(+), 8 deletions(-)
 rename rtl/{ => ppu}/ppu.sv (72%)

diff --git a/build/tb_top.Makefile b/build/tb_top.Makefile
index be9dd6c..6e73ff0 100644
--- a/build/tb_top.Makefile
+++ b/build/tb_top.Makefile
@@ -1,7 +1,7 @@
 TB       = tb_top
 SOURCES  = gb.sv cpu.sv ppu.sv idec.sv ctrl.sv alu.sv alu16.sv regbank.sv rom.sv ram.sv cart.sv tb_top.sv clkgen.sv
 INCLUDES = cpu_pkg.svh sva_common.svh
-PATH_SRC = ../rtl:../rtl/cpu:../sim
+PATH_SRC = ../rtl:../rtl/cpu:../rtl/ppu:../sim
 
 DEFINES = SVA_ENABLE
 
diff --git a/rtl/cpu/regbank.sv b/rtl/cpu/regbank.sv
index 3de6da7..fddcdd9 100644
--- a/rtl/cpu/regbank.sv
+++ b/rtl/cpu/regbank.sv
@@ -16,10 +16,8 @@ module regbank (
 
     input  reg8_t reg8_rselect_i,
     input  reg16_t reg16_rselect_i,
-    input  reg16_t reg16_rselect2_i,
     output logic [ 7:0] reg8_rdata_o,
     output logic [15:0] reg16_rdata_o,
-    output logic [15:0] reg16_rdata2_o,
 
     output logic [15:0] hl_o
 );
@@ -56,7 +54,6 @@ module regbank (
     assign reg8_rdata_o  = reg8_rselect_i[0] ? reg_r[reg8_rselect_i[2:1]][ 7:0] :
                                                reg_r[reg8_rselect_i[2:1]][15:8];
     assign reg16_rdata_o  = reg_r[reg16_rselect_i];
-    assign reg16_rdata2_o = reg_r[reg16_rselect2_i];
 
     assign hl_o = reg_r[REG16_HL];
 
diff --git a/rtl/ppu.sv b/rtl/ppu/ppu.sv
similarity index 72%
rename from rtl/ppu.sv
rename to rtl/ppu/ppu.sv
index 9eba262..8be9530 100644
--- a/rtl/ppu.sv
+++ b/rtl/ppu/ppu.sv
@@ -38,6 +38,12 @@ typedef struct packed {
 lcdc_t            lcdc;
 logic [3:0] [1:0] bgp;
 
+// LX is not read/writeable
+logic [ 8:0] lx_r;
+logic [ 8:0] lx_next;
+logic        lx_end_of_line;
+logic        ly_end_of_frame;
+
 `IOREG_DECL(lcdc);
 `IOREG_DECL(ly);
 `IOREG_DECL(sy);
@@ -54,16 +60,27 @@ assign  bgp_next = cpu_wdata_i;
 assign lcdc = lcdc_r;
 assign bgp  = bgp_r;
 
+
 always_ff @(posedge clk or negedge nreset) begin
-  if (!nreset)
+  if (!nreset) begin
     ly_r <= '0;
-  else
+    lx_r <= '0;
+  end else begin
     ly_r <= ly_next;
+    lx_r <= lx_next;
+  end
 end
 
 assign ly_sel  = (cpu_addr_i == 16'hFF44);
-assign ly_we   = ly_sel & cpu_we_i;
-assign ly_next = ly_we ? 8'h00 : 8'h90; // vsync hack
+assign ly_next = (ly_sel & cpu_we_i)                 ? 8'h00 : // Clear on write
+                 (lx_end_of_line &  ly_end_of_frame) ? 8'h00 :
+                 (lx_end_of_line & ~ly_end_of_frame) ? (ly_r + 8'h01) :
+                                                        ly_r;
+
+assign lx_next = lx_end_of_line ? 8'h0 : (lx_r + 8'h01);
+
+assign ly_end_of_frame = ly_r > 8'd153;
+assign lx_end_of_line  = lx_r > 9'd456;
 
 assign cpu_rdata_o =
   {8{lcdc_sel}} & lcdc_r |