WIP on PPU io registers

rtl/ppu.sv

@@ -8,20 +8,77 @@ module ppu (
   input  logic [ 7:0] cpu_wdata_i
 );
 
-logic        ly_sel;
-logic [ 7:0] ly_r;
-logic        ly_we;
+`define IOREG_DECL(name)    \
+  logic [ 7:0] name``_r;    \
+  logic [ 7:0] name``_next; \
+  logic        name``_we;   \
+  logic        name``_sel;
 
-assign ly_sel = (cpu_addr_i == 16'hFF44);
-assign ly_we  = ly_sel & cpu_we_i;
+`define IOREG_DEF(name, addr, rstval) \
+  always_ff @(posedge clk or negedge nreset) begin \
+    if (!nreset) \
+      name``_r <= rstval; \
+    else if (name``_we) \
+      name``_r <= name``_next; \
+  end \
+  assign name``_sel = (cpu_addr_i == addr); \
+  assign name``_we  = name``_we & cpu_we_i;
+
+typedef struct packed {
+  logic lcd_en;
+  logic win_tilemap_sel;
+  logic win_en;
+  logic tiledata_sel;
+  logic bg_tilemap_sel;
+  logic obj_size;
+  logic obj_display;
+  logic bgwin_display;
+} lcdc_t;
+
+lcdc_t            lcdc;
+logic [3:0] [1:0] bgp;
+
+`IOREG_DECL(lcdc);
+`IOREG_DECL(ly);
+`IOREG_DECL(sy);
+`IOREG_DECL(bgp);
+
+`IOREG_DEF    (lcdc, 16'hFF40, '0);
+`IOREG_DEF    (  sy, 16'hFF42, '0);
+`IOREG_DEF    ( bgp, 16'hFF47, '0);
+
+assign lcdc_next = cpu_wdata_i;
+assign   sy_next = cpu_wdata_i;
+assign  bgp_next = cpu_wdata_i;
+
+assign lcdc = lcdc_r;
+assign bgp  = bgp_r;
 
 always_ff @(posedge clk or negedge nreset) begin
   if (!nreset)
-    ly_r <= 8'h90; // vsync hack
-  else if (ly_we)
-    ly_r <= 8'h90;
+    ly_r <= '0;
+  else
+    ly_r <= ly_next;
 end
 
-assign cpu_rdata_o = {8{ly_sel}} & ly_r;
+assign ly_sel  = (cpu_addr_i == 16'hFF44);
+assign ly_we   = ly_sel & cpu_we_i;
+assign ly_next = ly_we ? 8'h00 : 8'h90; // vsync hack
+
+assign cpu_rdata_o =
+  {8{lcdc_sel}} & lcdc_r |
+  {8{  ly_sel}} &   ly_r |
+  {8{  sy_sel}} &   sy_r;
+
+`undef IOREG_DEF
+`undef IOREG_DECL
+
+`ifdef SVA_ENABLE
+
+logic sva_ppu_sel;
+
+assign sva_ppu_sel = lcdc_sel | ly_sel | sy_sel;
+
+`endif /* SVA_ENABLE */
 
 endmodule : ppu