WIP on PPU io registers
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7cec002e1a
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75
rtl/ppu.sv
75
rtl/ppu.sv
@ -8,20 +8,77 @@ module ppu (
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input logic [ 7:0] cpu_wdata_i
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input logic [ 7:0] cpu_wdata_i
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);
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);
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logic ly_sel;
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`define IOREG_DECL(name) \
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logic [ 7:0] ly_r;
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logic [ 7:0] name``_r; \
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logic ly_we;
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logic [ 7:0] name``_next; \
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logic name``_we; \
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logic name``_sel;
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assign ly_sel = (cpu_addr_i == 16'hFF44);
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`define IOREG_DEF(name, addr, rstval) \
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assign ly_we = ly_sel & cpu_we_i;
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always_ff @(posedge clk or negedge nreset) begin \
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if (!nreset) \
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name``_r <= rstval; \
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else if (name``_we) \
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name``_r <= name``_next; \
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end \
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assign name``_sel = (cpu_addr_i == addr); \
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assign name``_we = name``_we & cpu_we_i;
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typedef struct packed {
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logic lcd_en;
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logic win_tilemap_sel;
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logic win_en;
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logic tiledata_sel;
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logic bg_tilemap_sel;
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logic obj_size;
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logic obj_display;
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logic bgwin_display;
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} lcdc_t;
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lcdc_t lcdc;
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logic [3:0] [1:0] bgp;
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`IOREG_DECL(lcdc);
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`IOREG_DECL(ly);
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`IOREG_DECL(sy);
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`IOREG_DECL(bgp);
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`IOREG_DEF (lcdc, 16'hFF40, '0);
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`IOREG_DEF ( sy, 16'hFF42, '0);
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`IOREG_DEF ( bgp, 16'hFF47, '0);
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assign lcdc_next = cpu_wdata_i;
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assign sy_next = cpu_wdata_i;
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assign bgp_next = cpu_wdata_i;
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assign lcdc = lcdc_r;
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assign bgp = bgp_r;
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always_ff @(posedge clk or negedge nreset) begin
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always_ff @(posedge clk or negedge nreset) begin
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if (!nreset)
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if (!nreset)
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ly_r <= 8'h90; // vsync hack
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ly_r <= '0;
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else if (ly_we)
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else
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ly_r <= 8'h90;
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ly_r <= ly_next;
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end
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end
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assign cpu_rdata_o = {8{ly_sel}} & ly_r;
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assign ly_sel = (cpu_addr_i == 16'hFF44);
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assign ly_we = ly_sel & cpu_we_i;
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assign ly_next = ly_we ? 8'h00 : 8'h90; // vsync hack
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assign cpu_rdata_o =
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{8{lcdc_sel}} & lcdc_r |
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{8{ ly_sel}} & ly_r |
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{8{ sy_sel}} & sy_r;
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`undef IOREG_DEF
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`undef IOREG_DECL
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`ifdef SVA_ENABLE
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logic sva_ppu_sel;
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assign sva_ppu_sel = lcdc_sel | ly_sel | sy_sel;
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`endif /* SVA_ENABLE */
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endmodule : ppu
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endmodule : ppu
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@ -39,6 +39,12 @@ cart cart_inst (
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.data_io (gb_cart_data)
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.data_io (gb_cart_data)
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);
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);
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`ifdef SVA_ENABLE
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`include "sva_common.svh"
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`SVA_DEF_CLK(clk);
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`SVA_DEF_NRESET(nreset);
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logic instr_valid;
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logic instr_valid;
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logic instr_undef;
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logic instr_undef;
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logic halted;
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logic halted;
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@ -51,6 +57,7 @@ logic [ 7:0] last_write_value;
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logic vram_sel;
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logic vram_sel;
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logic hiram_sel;
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logic hiram_sel;
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logic ppu_sel;
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assign halted = gb_inst.cpu_inst.ctrl_inst.halted_r;
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assign halted = gb_inst.cpu_inst.ctrl_inst.halted_r;
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assign instr_valid = gb_inst.cpu_inst.instr_valid;
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assign instr_valid = gb_inst.cpu_inst.instr_valid;
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@ -61,6 +68,7 @@ assign we = gb_inst.cpu_we;
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assign vram_sel = gb_inst.vram_sel;
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assign vram_sel = gb_inst.vram_sel;
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assign hiram_sel = gb_inst.hiram_sel;
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assign hiram_sel = gb_inst.hiram_sel;
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assign ppu_sel = gb_inst.ppu_inst.sva_ppu_sel;
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always_ff @(posedge clk or negedge nreset) begin
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always_ff @(posedge clk or negedge nreset) begin
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if (!nreset)
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if (!nreset)
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@ -79,19 +87,14 @@ always_ff @(posedge clk or negedge nreset) begin
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end
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end
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end
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end
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// SVA code here
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`include "sva_common.svh"
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`SVA_DEF_CLK(clk);
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`SVA_DEF_NRESET(nreset);
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`SVA_ASSERT_PROP_FATAL(undefined_opcode_pushed,
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`SVA_ASSERT_PROP_FATAL(undefined_opcode_pushed,
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halted |-> !instr_undef,
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halted |-> !instr_undef,
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$sformatf("PC: 0x%X | Undefined opcode pushed: 0x%X (0x%X, 0x%X)", current_pc, current_opcode[0], current_opcode[1], current_opcode[2])
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$sformatf("PC: 0x%X | Undefined opcode pushed: 0x%X (0x%X, 0x%X)", current_pc, current_opcode[0], current_opcode[1], current_opcode[2])
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);
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);
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logic selected_memory_implemented;
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logic selected_memory_implemented;
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assign selected_memory_implemented = hiram_sel | vram_sel;
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assign selected_memory_implemented = hiram_sel | vram_sel | ppu_sel;
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`SVA_ASSERT_PROP(write_to_unimplemented_memory,
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`SVA_ASSERT_PROP(write_to_unimplemented_memory,
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we |-> selected_memory_implemented,
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we |-> selected_memory_implemented,
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@ -99,4 +102,5 @@ assign selected_memory_implemented = hiram_sel | vram_sel;
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current_pc, last_write_address, last_write_value)
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current_pc, last_write_address, last_write_value)
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);
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);
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`endif /* SVA_ENABLE */
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endmodule : tb_top
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endmodule : tb_top
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