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Initial register bank, support LD RR, $nnnn instructions

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This commit is contained in:
Koray Yanik
2021-02-17 22:40:24 +00:00
parent 237a5f1489
commit 2937ff492b
8 changed files with 163 additions and 36 deletions
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8
build/tb_top.Makefile
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@@ -2,8 +2,10 @@ TB = tb_top
SOURCES = gb.sv cpu.sv alu.sv registers.sv control.sv decode.sv rom.sv tb_top.sv clkgen.sv
PATH_SRC = ../rtl:../rtl/cpu:../rtl/shared:../sim/tbench:../sim/shared
gb.sdb: cpu.sdb rom.sdb
cpu.sdb: control.sdb registers.sdb alu.sdb
control.sdb: decode.sdb
gb.sdb: cpu.sdb rom.sdb cpu_pkg.sdb
cpu.sdb: control.sdb registers.sdb alu.sdb cpu_pkg.sdb
control.sdb: decode.sdb cpu_pkg.sdb
alu.sdb: cpu_pkg.sdb
registers.sdb: cpu_pkg.sdb
include ../synthflow/vivado/Makefile.rules