Initial register bank, support LD RR, $nnnn instructions

rtl/cpu/alu.sv

@@ -25,15 +25,6 @@ module alu (
     logic [ 7:0] a_xor;
     logic [ 7:0] f_xor;
 
-    `define DEF_FF(register, next, we, rst_value) \
-        always_ff @(posedge clk_i or negedge nreset_i) begin \
-            if (~nreset_i) begin \
-                register <= (rst_value); \
-            end else if ((we)) begin \
-                register <= (next); \
-            end \
-        end
-
     `DEF_FF(a_r, a_next, a_we, '0);
     `DEF_FF(f_r, f_next, f_we, '0);