Initial register bank, support LD RR, $nnnn instructions

rtl/cpu/cpu_pkg.svh

@@ -22,6 +22,13 @@ package cpu_pkg;
         REG8_L   = 3'h05
     } reg8_t;
 
+    typedef enum logic [1:0] {
+        REG16_BC    = 2'h00,
+        REG16_DE    = 2'h01,
+        REG16_HL    = 2'h02,
+        REG16_SP_AF = 2'h03
+    } reg16_t;
+
     typedef enum logic [2:0] {
         ALU_OP_ADD = 3'h00,
         ALU_OP_ADC = 3'h01,
@@ -35,15 +42,31 @@ package cpu_pkg;
 
     typedef enum {
         OP_SRC_A,
-        OP_SRC_REG8
+        OP_SRC_REG8,
+        OP_SRC_OPERAND16
     } op_src_t;
 
     typedef enum {
-        OP_DEST_A
+        OP_DEST_A,
+        OP_DEST_R16
     } op_dest_t;
 
     typedef enum {
         SP_SRC_OPERAND16
     } sp_src_t;
 
+    typedef enum {
+        ADR_SRC_PC,
+        ADR_SRC_HL
+    } adr_src_t;
+
 endpackage
+
+`define DEF_FF(register, next, we, rst_value) \
+    always_ff @(posedge clk_i or negedge nreset_i) begin \
+        if (~nreset_i) begin \
+            register <= (rst_value); \
+        end else if ((we)) begin \
+            register <= (next); \
+        end \
+    end