Initial register bank, support LD RR, $nnnn instructions

sim/tbench/tb_top.sv

@@ -13,5 +13,20 @@ module tb_top ();
         .nreset_i(nreset)
     );
 
+    // Testbench code
+    logic        instr_undef;
+    logic [15:0] last_pc;
+    logic [ 7:0] last_opcode;
+
+    assign instr_undef = gb_inst.cpu_inst.control_inst.is_undef;
+    assign last_pc     = gb_inst.cpu_inst.control_inst.instr_pc_r;
+    assign last_opcode = gb_inst.cpu_inst.control_inst.instr_r;
+
+    always @(posedge clk) begin
+        if (nreset && instr_undef) begin
+            $info($sformatf("[%t] %X: Undefined opcode %X", $time(), last_pc, last_opcode));
+            $fatal(0);
+        end
+    end
 
 endmodule : tb_top