From 3e92cf5eec6c1006200f8ba238306bc092fc01b4 Mon Sep 17 00:00:00 2001 From: Koray Yanik Date: Thu, 18 Feb 2021 09:27:17 +0000 Subject: [PATCH] Fix LD RR,$nnnn instruction not reading operand --- rtl/cpu/decode.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/cpu/decode.sv b/rtl/cpu/decode.sv index 5c37cf1..f7927d9 100644 --- a/rtl/cpu/decode.sv +++ b/rtl/cpu/decode.sv @@ -47,8 +47,8 @@ module decode ( assign is_alu_a_n = (dec_x == 3'h2); - assign need_instr1_o = is_ld_sp_nnnn; - assign need_instr2_o = is_ld_sp_nnnn; + assign need_instr1_o = is_ld_sp_nnnn | is_ld_rr_nnnn; + assign need_instr2_o = is_ld_sp_nnnn | is_ld_rr_nnnn; assign undef_o = ~(is_ld_sp_nnnn | is_ld_rr_nnnn | is_alu_a_n);