diff --git a/rtl/cpu/registers.sv b/rtl/cpu/registers.sv
index 5f76e56..e251d4e 100644
--- a/rtl/cpu/registers.sv
+++ b/rtl/cpu/registers.sv
@@ -31,9 +31,16 @@ module registers (
     generate for (genvar i = 0; i <= 2; i++) begin : gen_regs
         always_ff @(posedge clk_i or negedge nreset_i) begin
             if (~nreset_i) begin
-                reg_r[i] <= '0;
-            end else if (|reg_we[i]) begin
-                reg_r[i]<= reg_next;
+                reg_r[i][7:0] <= '0;
+            end else if (reg_we[i][0]) begin
+                reg_r[i][7:0] <= reg_next[7:0];
+            end
+        end
+        always_ff @(posedge clk_i or negedge nreset_i) begin
+            if (~nreset_i) begin
+                reg_r[i][15:8] <= '0;
+            end else if (reg_we[i][1]) begin
+                reg_r[i][15:8] <= reg_next[15:8];
             end
         end