diff --git a/rtl/cpu/decode.sv b/rtl/cpu/decode.sv
index 50d8048..83cc89d 100644
--- a/rtl/cpu/decode.sv
+++ b/rtl/cpu/decode.sv
@@ -38,7 +38,9 @@ module decode (
     logic is_ld_rr_nnnn;
     logic is_ld_sp_nnnn;
     logic is_ldd_hl_a;
-    logic is_alu_a_n;
+    logic is_alu_a_r;
+
+    reg8_t reg8_src;
 
     assign dec_x = instr0_i[7:6];
     assign dec_y = instr0_i[5:3];
@@ -50,33 +52,35 @@ module decode (
     assign is_ld_sp_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p == 2'h3);
     assign is_ldd_hl_a   = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h3);
 
-    assign is_alu_a_n = (dec_x == 3'h2);
+    assign is_alu_a_r = (dec_x == 3'h2);
 
     assign need_instr1_o = is_ld_sp_nnnn | is_ld_rr_nnnn;
     assign need_instr2_o = is_ld_sp_nnnn | is_ld_rr_nnnn;
 
-    assign undef_o = ~(is_ld_sp_nnnn | is_ld_rr_nnnn | is_alu_a_n | is_ldd_hl_a);
+    assign undef_o = ~(is_ld_sp_nnnn | is_ld_rr_nnnn | is_alu_a_r | is_ldd_hl_a);
 
     assign sp_we_o  = is_ld_sp_nnnn & (state_i == ST4_EXEC);
 
-    assign alu_op_valid_o = is_alu_a_n;
     assign alu_op_o       = alu_op_t'(dec_y);
-    assign op_dest_o      = is_alu_a_n    ? OP_DEST_A     :
-                            is_ld_rr_nnnn ? OP_DEST_REG16 :
+    assign alu_op_valid_o = is_alu_a_r;
+
+    assign op_dest_o      = is_ld_rr_nnnn ? OP_DEST_REG16 :
                             is_ldd_hl_a   ? OP_DEST_REG16 :
                                             op_dest_t'('X);
 
-    assign op_src_o       = is_alu_a_n    ? OP_SRC_REG8      :
-                            is_ld_rr_nnnn ? OP_SRC_OPERAND16 :
-                            is_ldd_hl_a   ? OP_SRC_REG16     :
-                                            op_src_t'('X);
+    assign op_src_o       = (is_alu_a_r & reg8_src == REG8_A) ? OP_SRC_A         :
+                            (is_alu_a_r & reg8_src != REG8_A) ? OP_SRC_REG8      :
+                            is_ld_rr_nnnn                     ? OP_SRC_OPERAND16 :
+                            is_ldd_hl_a                       ? OP_SRC_REG16     :
+                                                                op_src_t'('X);
 
+    assign reg8_src_o   = reg8_src;
     assign reg16_src_o  = is_ldd_hl_a ? REG16_HL : reg16_t'(dec_p);
-    assign reg16_dest_o = is_ldi_hl_a ? REG16_HL : reg16_t'(dec_p);
+    assign reg16_dest_o = is_ldd_hl_a ? REG16_HL : reg16_t'(dec_p);
 
-    assign adr_src_o = is_ldi_hl_a ? ADR_SRC_HL :
+    assign adr_src_o = is_ldd_hl_a ? ADR_SRC_HL :
                                      ADR_SRC_PC;
 
-    assign memory_we_o = is_ldi_hl_a;
+    assign memory_we_o = is_ldd_hl_a;
 
-endmodule : decode
\ No newline at end of file
+endmodule : decode