diff --git a/rtl/cpu/registers.sv b/rtl/cpu/registers.sv
index e251d4e..fff95c4 100644
--- a/rtl/cpu/registers.sv
+++ b/rtl/cpu/registers.sv
@@ -44,10 +44,10 @@ module registers (
             end
         end
 
-        assign reg_we[i][0] = (reg16_we_i & (reg16_wselect_i == i)) |
-                              (reg8_we_i  & ({reg8_wselect_i, 1'b0} == i));
-        assign reg_we[i][1] = (reg16_we_i & (reg16_wselect_i == i)) |
-                              (reg8_we_i  & ({reg8_wselect_i, 1'b1} == i));
+        assign reg_we[i][0] = (reg16_we_i & (reg16_wselect_i == i[1:0])) |
+                              (reg8_we_i  & (reg8_wselect_i  == {i[1:0], 1'b0}));
+        assign reg_we[i][1] = (reg16_we_i & (reg16_wselect_i == i[1:0])) |
+                              (reg8_we_i  & (reg8_wselect_i  == {i[1:0], 1'b1}));
     end endgenerate
 
     assign reg_next = ({16{reg8_we_i}}  & {reg8_wdata_i, reg8_wdata_i}) |