From b1b2055db9ee63111b87dd232677abe14df733d2 Mon Sep 17 00:00:00 2001 From: Koray Yanik Date: Sat, 20 Feb 2021 20:52:02 +0000 Subject: [PATCH] Fix another bug in 8bit register writing --- rtl/cpu/registers.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/rtl/cpu/registers.sv b/rtl/cpu/registers.sv index e251d4e..fff95c4 100644 --- a/rtl/cpu/registers.sv +++ b/rtl/cpu/registers.sv @@ -44,10 +44,10 @@ module registers ( end end - assign reg_we[i][0] = (reg16_we_i & (reg16_wselect_i == i)) | - (reg8_we_i & ({reg8_wselect_i, 1'b0} == i)); - assign reg_we[i][1] = (reg16_we_i & (reg16_wselect_i == i)) | - (reg8_we_i & ({reg8_wselect_i, 1'b1} == i)); + assign reg_we[i][0] = (reg16_we_i & (reg16_wselect_i == i[1:0])) | + (reg8_we_i & (reg8_wselect_i == {i[1:0], 1'b0})); + assign reg_we[i][1] = (reg16_we_i & (reg16_wselect_i == i[1:0])) | + (reg8_we_i & (reg8_wselect_i == {i[1:0], 1'b1})); end endgenerate assign reg_next = ({16{reg8_we_i}} & {reg8_wdata_i, reg8_wdata_i}) |