diff --git a/rtl/cpu/cpu.sv b/rtl/cpu/cpu.sv
index 1dcbc28..d5a95e3 100644
--- a/rtl/cpu/cpu.sv
+++ b/rtl/cpu/cpu.sv
@@ -114,6 +114,7 @@ module cpu (
     );
 
     assign alu_operand = (op_src == OP_SRC_A)        ? rega       :
+                         (op_src == OP_SRC_F)        ? regf       :
                          (op_src == OP_SRC_OPERAND8) ? operand8   :
                          (op_src == OP_SRC_REG8)     ? reg8_rdata :
                          (op_src == OP_SRC_MEMORY)   ? rdata_i    :
diff --git a/rtl/cpu/cpu_pkg.svh b/rtl/cpu/cpu_pkg.svh
index 4e34027..f077b75 100644
--- a/rtl/cpu/cpu_pkg.svh
+++ b/rtl/cpu/cpu_pkg.svh
@@ -63,6 +63,7 @@ package cpu_pkg;
 
     typedef enum {
         OP_SRC_A,
+        OP_SRC_F,
         OP_SRC_REG8,
         OP_SRC_OPERAND8,
         OP_SRC_MEMORY,
diff --git a/rtl/cpu/decode.sv b/rtl/cpu/decode.sv
index a1463ff..d460f01 100644
--- a/rtl/cpu/decode.sv
+++ b/rtl/cpu/decode.sv
@@ -62,9 +62,11 @@ module decode (
     logic is_inc_r;
     logic is_jr_cc_n;
     logic is_call_nn;
+    logic is_push_rr;
 
     reg8_t reg8_dest;
     reg8_t reg8_src;
+    reg16_t reg16_src;
 
     assign dec_x = instr0_i[7:6];
     assign dec_y = instr0_i[5:3];
@@ -95,23 +97,30 @@ module decode (
 
     assign is_jr_cc_n = (dec_x == 2'h0) & (dec_z == 2'h0) & dec_y[2];
     assign is_call_nn = (instr0_i == 8'hCD);
+    assign is_push_rr = (dec_x == 2'h3) & (dec_z == 3'h5) && ~dec_q;
 
-    assign reg8_src = is_cb      ? reg8_t'(instr1_i[2:0]) :
-                      is_ldh_c_a ? REG8_C                 :
-                      is_inc_r   ? reg8_t'(dec_y)         :
-                                   reg8_t'(dec_z);
+    assign reg8_src = is_cb                              ? reg8_t'(instr1_i[2:0]) :
+                      is_ldh_c_a                         ? REG8_C                 :
+                      is_inc_r                           ? reg8_t'(dec_y)         :
+                      (is_push_rr & state_i == ST2_EXEC) ? reg8_t'({dec_p, 1'b0})  :
+                      (is_push_rr & state_i == ST3_EXEC) ? reg8_t'({dec_p, 1'b1})  :
+                                                           reg8_t'(dec_z);
     assign reg8_dest = reg8_t'(dec_y);
 
+    assign reg16_src = is_ldd_hl_a ? REG16_HL : reg16_t'(dec_p);
+
     assign need_instr1_o   = is_ld_sp_nn | is_ld_rr_nn | is_ld_a_nn | is_call_nn | is_cb | is_jr_cc_n | is_ld_r_n | is_ldh_n_a;
     assign need_instr2_o   = is_ld_sp_nn | is_ld_rr_nn | is_ld_a_nn | is_call_nn;
-    assign is_multicycle_o = is_ld_a_rr | is_call_nn;
+    assign is_multicycle_o = is_ld_a_rr | is_call_nn | is_push_rr;
 
     assign undef_o = ~(is_ldh_n_a | is_ld_r_r | is_ld_sp_nn | is_ld_rr_nn | is_alu_a_r | is_ldd_hl_a | is_bit_n_r |
-                       is_jr_cc_n | is_ld_r_n | is_ldh_c_a  | is_inc_r    | is_ld_rr_a | is_ld_a_rr | is_call_nn);
+                       is_jr_cc_n | is_ld_r_n | is_ldh_c_a  | is_inc_r    | is_ld_rr_a | is_ld_a_rr  | is_call_nn |
+                       is_push_rr);
 
-    assign sp_we_o  = is_ld_sp_nn | is_call_nn;
+    assign sp_we_o  = is_ld_sp_nn | is_call_nn | is_push_rr;
     assign sp_src_o = is_ld_sp_nn ? SP_SRC_OPERAND16 :
                       is_call_nn  ? SP_SRC_DEC       :
+                      is_push_rr  ? SP_SRC_DEC       :
                                     sp_src_t'('X);
 
     assign alu_op_valid_o = is_alu_a_r | is_bit_n_r | is_ld_a_n | is_ld_a_rr | is_ld_a_nn | is_inc_r;
@@ -139,6 +148,7 @@ module decode (
                             is_inc_a                            ? OP_DEST_A      :
                             is_inc_r                            ? OP_DEST_REG8   :
                             is_call_nn                          ? OP_DEST_MEMORY :
+                            is_push_rr                          ? OP_DEST_MEMORY :
                                                                   op_dest_t'('X);
 
     assign op_src_o       = (is_ld_r_r  & reg8_src == REG8_A)   ? OP_SRC_A         :
@@ -154,14 +164,17 @@ module decode (
                             is_ld_rr_nn                         ? OP_SRC_OPERAND16 :
                             is_ldd_hl_a                         ? OP_SRC_REG16     :
                             is_bit_n_r                          ? OP_SRC_REG8      :
-                            is_call_nn & (state_i == ST4_EXEC)  ? OP_SRC_PC_L      :
-                            is_call_nn & (state_i == ST5_EXEC)  ? OP_SRC_PC_H      :
+                            (is_call_nn & state_i == ST4_EXEC)  ? OP_SRC_PC_L      :
+                            (is_call_nn & state_i == ST5_EXEC)  ? OP_SRC_PC_H      :
+                            (is_push_rr & reg16_src != REG16_SP_AF) ? OP_SRC_REG8  :
+                            (is_push_rr & reg16_src == REG16_SP_AF & state_i == ST2_EXEC) ? OP_SRC_A  :
+                            (is_push_rr & reg16_src == REG16_SP_AF & state_i == ST3_EXEC) ? OP_SRC_F  :
                                                                   op_src_t'('X);
 
     assign reg8_dest_o  = reg8_dest;
     assign reg8_src_o   = reg8_src;
-    assign reg16_src_o  = is_ldd_hl_a ? REG16_HL : reg16_t'(dec_p);
-    assign reg16_dest_o = is_ldd_hl_a ? REG16_HL : reg16_t'(dec_p);
+    assign reg16_src_o  = reg16_src;
+    assign reg16_dest_o = reg16_src;
 
     assign pc_src_o = is_jr_cc_n ? PC_SRC_OPERAND8  :
                       is_call_nn ? PC_SRC_OPERAND16 :
@@ -178,11 +191,13 @@ module decode (
                        is_ld_a_rr                          ? ADR_SRC_REG16     :
                        is_ld_rr_a                          ? ADR_SRC_REG16     :
                        is_call_nn                          ? ADR_SRC_SP        :
+                       is_push_rr                          ? ADR_SRC_SP        :
                                                              ADR_SRC_PC;
 
     assign branch_always_o = is_call_nn;
     assign cc_o = cc_t'(dec_y[1:0]);
 
-    assign memory_we_o = is_ldd_hl_a | is_ldh_c_a | is_ldh_n_a | is_ld_rr_a | (is_ld_r_n & reg8_dest == REG8_PHL) | (is_ld_r_r & reg8_dest == REG8_PHL) | is_call_nn;
+    assign memory_we_o = is_ldd_hl_a | is_ldh_c_a | is_ldh_n_a | is_ld_rr_a | (is_ld_r_n & reg8_dest == REG8_PHL) | (is_ld_r_r & reg8_dest == REG8_PHL) |
+                         is_call_nn  | is_push_rr;
 
 endmodule : decode