diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..d9ca403
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+build/.Xil
+build/xsim.dir
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..f9b8d0c
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "synthflow"]
+	path = synthflow
+	url = gitea:fumyuun/synthflow.git
diff --git a/build/tb_top.Makefile b/build/tb_top.Makefile
new file mode 100644
index 0000000..8114232
--- /dev/null
+++ b/build/tb_top.Makefile
@@ -0,0 +1,5 @@
+TB       = tb_top
+SOURCES  = gb.sv tb_top.sv
+PATH_SRC = ../rtl:../sim/tbench
+
+include ../synthflow/vivado/Makefile.rules
\ No newline at end of file
diff --git a/rtl/gb.sv b/rtl/gb.sv
new file mode 100644
index 0000000..1f695ae
--- /dev/null
+++ b/rtl/gb.sv
@@ -0,0 +1,8 @@
+module gb (
+    input  logic clk_i,
+    input  logic nreset_i
+);
+
+
+
+endmodule : gb
diff --git a/sim/tbench/tb_top.sv b/sim/tbench/tb_top.sv
new file mode 100644
index 0000000..3827e5c
--- /dev/null
+++ b/sim/tbench/tb_top.sv
@@ -0,0 +1,21 @@
+module tb_top ();
+
+    logic clk;
+    logic nreset;
+
+    gb gb_inst (
+        .clk_i   (clk),
+        .nreset_i(nreset)
+    );
+
+    initial begin
+        clk    = 1'b0;
+        nreset = 1'b1;
+
+        #1  nreset = 1'b0;
+        #24 nreset = 1'b1;
+    end // initial
+
+    always #5 clk = ~clk;
+
+endmodule : tb_top
diff --git a/synthflow b/synthflow
new file mode 160000
index 0000000..767277e
--- /dev/null
+++ b/synthflow
@@ -0,0 +1 @@
+Subproject commit 767277e341012aa54acd72d26be9ea2fc921ca0c