Complete rewrite from scratch, bootstrap WIP

Rewrite to use several bus multiplexers, resulting into a less messy
microarchitecture (hopefully). Some more room for cleanup though...

Supports every instruction from the bootstrap rom, more or less.
LY hacked at 0x90 to progress through vsync instantly.
No cartridge is present yet, so we will always fail checksum test and lock up.

build/tb_top.Makefile

@@ -1,7 +1,8 @@
 TB       = tb_top
-SOURCES  = gb.sv cpu.sv alu.sv registers.sv control.sv decode.sv rom.sv ram.sv tb_top.sv clkgen.sv
-INCLUDES = cpu_pkg.svh
-PATH_SRC = ../rtl:../rtl/cpu:../rtl/shared:../sim/tbench:../sim/shared
+SOURCES  = gb.sv cpu.sv ppu.sv idec.sv ctrl.sv alu.sv alu16.sv regbank.sv rom.sv ram.sv tb_top.sv clkgen.sv
+INCLUDES = cpu_pkg.svh sva_common.svh
+PATH_SRC = ../rtl:../rtl/cpu:../sim
+
+DEFINES = SVA_ENABLE
 
 include ../synthflow/vivado/Makefile.rules
-