// Top level gb module
module gb (
  input  wire clk,
  input  wire nreset,

  // Cartridge bus
  output  wire        cart_clk_o,
  output  wire        cart_nreset_o,
  output  wire        cart_nrd_o,
  output  wire        cart_nwr_o,
  output  wire        cart_ncs_o,
  output  wire [15:0] cart_addr_o,
  inout   wire [ 7:0] cart_data_io,

  // PPU output to display
  output logic        ppu_display_enable_o,
  output logic [ 1:0] ppu_pixel_o,
  output logic        ppu_vsync_o,
  output logic        ppu_hsync_o

);

logic [15:0] cpu_addr;
logic [ 7:0] cpu_rdata;
logic        cpu_we;
logic [ 7:0] cpu_wdata;

logic [ 7:0] cpu_ppu_rdata;

logic        rom_enable_r;
logic        rom_sel;
logic [ 7:0] rom_rdata;
logic        hiram_sel;
logic [ 7:0] hiram_rdata;
logic        vram_sel;
logic [ 7:0] vram_rdata;
logic        cart_sel;
logic [ 7:0] cart_rdata;

cpu cpu_inst (
  .clk    (clk),
  .nreset (nreset),

  .addr_o (cpu_addr),
  .rdata_i(cpu_rdata),
  .we_o   (cpu_we),
  .wdata_o(cpu_wdata)
);

ppu ppu_inst (
  .clk    (clk),
  .nreset (nreset),

  .display_enable_o(ppu_display_enable_o),

  .cpu_addr_i (cpu_addr),
  .cpu_rdata_o(cpu_ppu_rdata),
  .cpu_we_i   (cpu_we),
  .cpu_wdata_i(cpu_wdata),

  .pixel_o    (ppu_pixel_o),
  .vsync_o    (ppu_vsync_o),
  .hsync_o    (ppu_hsync_o)
);

assign rom_enable_r = '1;

assign rom_sel   = rom_enable_r & ~(|cpu_addr[15:8]);
assign vram_sel  = (cpu_addr[15:13] == 3'b100);
assign hiram_sel = (&cpu_addr[15:7]) & ~(&cpu_addr[6:0]);
assign cart_sel  = (~cpu_addr[15]) & (~cpu_addr[14]) & (~rom_sel);

assign cpu_rdata = rom_rdata     |
                   vram_rdata    |
                   hiram_rdata   |
                   cpu_ppu_rdata |
                   cart_rdata;

rom #(
  .FILE_NAME("DMG_ROM.bin"),
  .ADDR_W   (8),
  .DATA_W   (8)
) rom_inst (
  .clk      (clk),
  .nreset   (nreset),
  .cs_i     (rom_sel),
  .address_i(cpu_addr[7:0]),
  .rdata_o  (rom_rdata)
);

ram #(
  .ADDR_W   (13),
  .DATA_W   (8)
) vram_inst (
  .clk       (clk),
  .nreset    (nreset),
  .cs_i      (vram_sel),
  .address_i (cpu_addr[12:0]),
  .rdata_o   (vram_rdata),
  .we_i      (cpu_we),
  .wdata_i   (cpu_wdata)
);

ram #(
  .ADDR_W (7),
  .DATA_W (8)
) hiram_inst (
  .clk       (clk),
  .nreset    (nreset),
  .cs_i      (hiram_sel),
  .address_i (cpu_addr[6:0]),
  .rdata_o   (hiram_rdata),
  .we_i      (cpu_we),
  .wdata_i   (cpu_wdata)
);

assign cart_rdata = cart_sel ? cart_data_io : '0;

assign cart_clk_o    = clk;
assign cart_nreset_o = nreset;
assign cart_nrd_o    = 1'b0;
assign cart_nwr_o    = 1'b1;
assign cart_ncs_o    = ~cart_sel;
assign cart_addr_o   = cpu_addr;

endmodule : gb