module clkgen #(
PERIOD_NS      = 10,
RESET_DELAY_NS = 45
) (
  output logic clk,
  output logic nreset
);

initial begin
  clk    = 1'b1;
  nreset = 1'b0;
  #RESET_DELAY_NS nreset = 1'b1;
end

always
  #(PERIOD_NS/2) clk <= ~clk;

endmodule