`include "cpu_pkg.svh"

import cpu_pkg::*;

module control (
    input  logic   clk_i,
    input  logic   nreset_i,
    output state_t state_o,

    output logic [15:0] pc_o
);

    state_t state_r;
    state_t state_next;

    logic        pc_we;
    logic [15:0] pc_r;
    logic [15:0] pc_next;

    always_ff @(posedge clk_i or negedge nreset_i) begin
        if (~nreset_i)
            state_r <= ST0_ADDR;
        else
            state_r <= state_next;
    end

    always_ff @(posedge clk_i or negedge nreset_i) begin
        if (~nreset_i)
            pc_r <= '0;
        else if (pc_we)
            pc_r <= pc_next;
    end

    assign pc_we   = (state_r == ST0_ADDR);
    assign pc_next = (pc_r + 16'b1);

    always_comb begin
        case (state_r)
            ST0_ADDR:     state_next = ST1_DEC;
            ST1_DEC:      state_next = ST2_EXEC;
            ST2_EXEC:     state_next = ST3_INC_ADDR;
            ST3_INC_ADDR: state_next = ST0_ADDR;
        endcase
    end

    assign state_o = state_r;
    assign pc_o    = pc_r;

endmodule : control