module clkgen #(
    PERIOD_NS      = 10,
    RESET_DELAY_NS = 100
) (
    output logic clk_o,
    output logic nreset_o
);

    initial begin
        clk_o    <= 1'b0;
        nreset_o <= 1'b0;
        #RESET_DELAY_NS nreset_o <= 1'b1;
    end

    always
        #(PERIOD_NS/2) clk_o <= ~clk_o;

endmodule